General question on the simulation of VHDL-code with Alteras QuartusII

Discussion in 'VHDL' started by Markus Jochim, Jun 6, 2007.

  1. Hello everybody,

    I just started with VHDL and I have three (probably simple) questions:

    Using Alteras Quartus 2 Tool I want to do some VHDL simulation:

    A simple example:

    ARCHITECTURE TEST OF TEST IS
    BEGIN
    x <= i after 20 ns;
    END TEST;

    Using the simulator that is integrated in Quartus 2 I generated a simple
    waveform where:

    i = ' 0 ' form 0 ns to 10 ns
    i = ' 1 ' for time > 10 ns

    When I switch to "Functional Simulation" timing is ignored (as
    expected). When I switch to "Timing Simulation" I get:

    x = '1' for time > 23 ns

    which obviously reflects the timing of the FPGA for which the design was
    synthesised by Quartus II.

    Now my questions are as follows:

    Question 1: How can I just perform a VHDL simulation that reflects the
    timing expressed by the statement "... after 20 ns"?

    Question 2: How can I instruct Quartus II to accept all valid VHDL-code
    and not only code that actually can be synthesised? I just want to
    simulate a VHDL model!

    Question 3: How can run simple test benches written in VHDL (like in the
    example attached below) and watch the resulting waveforms using Quartus II.

    Any help is highly appreciated!

    Best regards

    Markus




    -- Test Bench:

    LIBRARY IEEE;
    USE IEEE.std_logic_1164.ALL;

    ENTITY TEST IS
    PORT (
    i1, i2: IN std_logic;
    o: OUT std_logic
    );
    END TEST;


    ARCHITECTURE TEST OF TEST IS
    BEGIN
    o <= i1 and i2;
    END TEST;



    LIBRARY IEEE;
    USE IEEE.std_logic_1164.ALL;

    ENTITY TB_TEST IS
    END TB_TEST;

    ARCHITECTURE TB_TEST of TB_TEST is
    COMPONENT TEST IS
    PORT (
    i1, i2: IN std_logic;
    o: OUT std_logic
    );
    END COMPONENT;

    SIGNAL w_i1, w_i2: std_logic;
    BEGIN
    DUT:
    TEST PORT MAP( i1 => w_i1,
    i2 => w_i2);

    STIMULI:
    PROCESS
    BEGIN
    w_i1 <= '1';
    WAIT FOR 50 ns;
    w_i2 <= '1';
    WAIT FOR 50 ns;
    w_i1 <= '0';
    WAIT FOR 50 ns;
    END PROCESS STIMULI;
    END TB_TEST;
     
    Markus Jochim, Jun 6, 2007
    #1
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  2. Re: General question on the simulation of VHDL-code with AlterasQuartus II

    Markus Jochim wrote:

    > Using Alteras Quartus 2 Tool I want to do some VHDL simulation:
    > A simple example:
    > ARCHITECTURE TEST OF TEST IS
    > BEGIN
    > x <= i after 20 ns;
    > END TEST;
    > Using the simulator that is integrated in Quartus 2 I generated a simple
    > waveform where:


    The integrated simulator is not a vhdl simulator.
    Use the quartus oem modelsim program instead.

    -- Mike Treseler
     
    Mike Treseler, Jun 6, 2007
    #2
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  3. Markus Jochim

    Guest

    Re: General question on the simulation of VHDL-code with Alteras Quartus II

    On Jun 6, 11:14 am, Markus Jochim <-due.de> wrote:
    > Hello everybody,
    >
    > I just started with VHDL and I have three (probably simple) questions:
    >
    > Using Alteras Quartus 2 Tool I want to do some VHDL simulation:
    >
    > A simple example:
    >
    > ARCHITECTURE TEST OF TEST IS
    > BEGIN
    > x <= i after 20 ns;
    > END TEST;
    >
    > Using the simulator that is integrated in Quartus 2 I generated a simple
    > waveform where:
    >
    > i = ' 0 ' form 0 ns to 10 ns
    > i = ' 1 ' for time > 10 ns
    >
    > When I switch to "Functional Simulation" timing is ignored (as
    > expected). When I switch to "Timing Simulation" I get:
    >
    > x = '1' for time > 23 ns
    >
    > which obviously reflects the timing of the FPGA for which the design was
    > synthesised by Quartus II.
    >
    > Now my questions are as follows:
    >
    > Question 1: How can I just perform a VHDL simulation that reflects the
    > timing expressed by the statement "... after 20 ns"?
    >
    > Question 2: How can I instruct Quartus II to accept all valid VHDL-code
    > and not only code that actually can be synthesised? I just want to
    > simulate a VHDL model!
    >
    > Question 3: How can run simple test benches written in VHDL (like in the
    > example attached below) and watch the resulting waveforms using Quartus II.
    >
    > Any help is highly appreciated!
    >
    > Best regards
    >
    > Markus
    >
    > -- Test Bench:
    >
    > LIBRARY IEEE;
    > USE IEEE.std_logic_1164.ALL;
    >
    > ENTITY TEST IS
    > PORT (
    > i1, i2: IN std_logic;
    > o: OUT std_logic
    > );
    > END TEST;
    >
    > ARCHITECTURE TEST OF TEST IS
    > BEGIN
    > o <= i1 and i2;
    > END TEST;
    >
    > LIBRARY IEEE;
    > USE IEEE.std_logic_1164.ALL;
    >
    > ENTITY TB_TEST IS
    > END TB_TEST;
    >
    > ARCHITECTURE TB_TEST of TB_TEST is
    > COMPONENT TEST IS
    > PORT (
    > i1, i2: IN std_logic;
    > o: OUT std_logic
    > );
    > END COMPONENT;
    >
    > SIGNAL w_i1, w_i2: std_logic;
    > BEGIN
    > DUT:
    > TEST PORT MAP( i1 => w_i1,
    > i2 => w_i2);
    >
    > STIMULI:
    > PROCESS
    > BEGIN
    > w_i1 <= '1';
    > WAIT FOR 50 ns;
    > w_i2 <= '1';
    > WAIT FOR 50 ns;
    > w_i1 <= '0';
    > WAIT FOR 50 ns;
    > END PROCESS STIMULI;
    > END TB_TEST;


    To expand on Mike's answer:

    Question 1: Use a real simulator.
    Question 2: You can't; Quartus is essentially a front end for a
    synthesizer (Use a real simulator.)
    Question 3: Use a real simulator.
     
    , Jun 7, 2007
    #3
  4. Markus Jochim

    HT-Lab Guest

    Re: General question on the simulation of VHDL-code with Alteras Quartus II

    <> wrote in message
    news:...
    > On Jun 6, 11:14 am, Markus Jochim <-due.de> wrote:
    >> Hello everybody,
    >>
    >> I just started with VHDL and I have three (probably simple) questions:
    >>
    >> Using Alteras Quartus 2 Tool I want to do some VHDL simulation:
    >>
    >> A simple example:
    >>
    >> ARCHITECTURE TEST OF TEST IS
    >> BEGIN
    >> x <= i after 20 ns;
    >> END TEST;
    >>
    >> Using the simulator that is integrated in Quartus 2 I generated a simple
    >> waveform where:
    >>
    >> i = ' 0 ' form 0 ns to 10 ns
    >> i = ' 1 ' for time > 10 ns
    >>
    >> When I switch to "Functional Simulation" timing is ignored (as
    >> expected). When I switch to "Timing Simulation" I get:
    >>
    >> x = '1' for time > 23 ns
    >>
    >> which obviously reflects the timing of the FPGA for which the design was
    >> synthesised by Quartus II.
    >>
    >> Now my questions are as follows:
    >>
    >> Question 1: How can I just perform a VHDL simulation that reflects the
    >> timing expressed by the statement "... after 20 ns"?
    >>
    >> Question 2: How can I instruct Quartus II to accept all valid VHDL-code
    >> and not only code that actually can be synthesised? I just want to
    >> simulate a VHDL model!
    >>
    >> Question 3: How can run simple test benches written in VHDL (like in the
    >> example attached below) and watch the resulting waveforms using Quartus
    >> II.

    ...snip..
    >
    > To expand on Mike's answer:
    >
    > Question 1: Use a real simulator.
    > Question 2: You can't; Quartus is essentially a front end for a
    > synthesizer (Use a real simulator.)
    > Question 3: Use a real simulator.


    So if I understand you correctly, you are trying to say that he should use a
    real simulator? :)

    Hans
    www.ht-lab.com
     
    HT-Lab, Jun 8, 2007
    #4
  5. Re: General question on the simulation of VHDL-code with AlterasQuartus II

    That was my impression as well... I tried the ModelSim Web Edition as
    recommended by Mike and everything works fine!

    Thanks for answering a Newbie-question and for being helpful with a
    simple and unambiguous answer ;-)

    Markus

    >
    > So if I understand you correctly, you are trying to say that he should use a
    > real simulator? :)
    >
    > Hans
    > www.ht-lab.com
    >
    >
    >
     
    Markus Jochim, Jun 8, 2007
    #5
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