Generate component

Discussion in 'VHDL' started by kmponis, Sep 29, 2010.

  1. kmponis

    kmponis

    Joined:
    Sep 29, 2010
    Messages:
    3
    Helloooo

    I would like to know if i can generate an entity into a process ?

    Im doing this :

    PROCESS
    BEGIN

    gen_modul: for j in 0 to 63 loop

    d_mem : d_mem_131072x16 PORT MAP (clk,"0000000000000000",addr,'0',d_mem_out);


    end loop gen_modul;

    END PROCESS;


    And I have an ERROR : parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
     
    kmponis, Sep 29, 2010
    #1
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  2. kmponis

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    Uhmm no you can't do this inside a process.
    Though you can use for-generate and if-generate;


    constant zero : std_logic_vector(15 downto 0) := (others => '0');

    gen_modul: for j in 0 to 63 generate
    d_mem : d_mem_131072x16 PORT MAP (clk,zero,addr,zero(0),d_mem_out);
    end generate gen_modul;
     
    joris, Sep 29, 2010
    #2
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  3. kmponis

    kmponis

    Joined:
    Sep 29, 2010
    Messages:
    3
    Thanks Joris thats working !!

    Actually i want to read continueing blocks of the memory and edit the prices im getting !!

    Can you help me with this because i think with generate loop i cant do something like this !
     
    kmponis, Oct 1, 2010
    #3
  4. kmponis

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    Uhm can't you do this inside a process to handle the results you got from the memory component ? The process should probably be clocked as the memory is as well.
     
    joris, Oct 1, 2010
    #4
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