generate statements with complex connection logic

Discussion in 'VHDL' started by wallge, Feb 24, 2006.

  1. wallge

    wallge Guest

    when doing a series of nested if ... generate and for ... generate
    statements,

    the only sort of "book-keeping variables" that can be used to control
    connection of block A to block B seem to be the loop indices
    themselves.
    I have found that you can call custom functions that can return other
    values based on loop indices or constants / generics. Is this the only
    way
    to have a sense of "book-keeping" variables that may be needed when
    doing complex
    component generate statements? (a genericly-sized, pipelined matrix (m
    x k, k x n) multiply, or 2d convolution (m x n)
    is a good example of the need for complex generate statements)
    wallge, Feb 24, 2006
    #1
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  2. wallge wrote:
    > when doing a series of nested if ... generate and for ... generate
    > statements,
    > the only sort of "book-keeping variables" that can be used to control
    > connection of block A to block B seem to be the loop indices
    > themselves. I have found that you can call custom functions that can return other
    > values based on loop indices or constants / generics.
    > Is this the only way
    > to have a sense of "book-keeping" variables that may be needed when
    > doing complex component generate statements?


    I agree that complex generate statements are annoying.
    I prefer to declare array subtypes in a single process
    as shown below.

    -- Mike Treseler
    __________________________
    subtype stat_reg_t is unsigned (cnt_len-1 downto 0);
    -- 32 bit register
    type cnt_reg_t is array(1 to 2) of stat_reg_t; -- counter/reg pair
    type err_cnt_t is array(error_descriptor) of cnt_reg_t;
    -- each error type gets a counter/reg
    variable err_cnt : err_cnt_t;
    variable octet_cnt : cnt_reg_t;
    Mike Treseler, Feb 26, 2006
    #2
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