generate stimulus in a 'do' file

[Guy_Sweden]

Hello there.
I am trying to simulate the vga interface wherein the data (pixel
information) is read and formatted and then put on the screen in order
to reproduce the picture which is stored in the form of consecutive
pixels in a SRAM.

one of the modules in the interface sends the address to the SRAM
which then sends it the data (pixel) at that mem location. And certain
operations are to be help until we have received the pixl from the
SRAM. Theres one module which then receives the data from the SRAM and
then reformats it before sending it to the electron RGB guns which
then generate the color according to the information in that data.

Now before burning it to an actual FPGA, i wanna test if all the
timing criteria are being met elsewhere.

So when the module (entity) sends the address to be sent out to the
SRAM, i want to generate a 16 bit vector in response and send that to
the input of the entity which expects the data on the input.
In order to do that i thought i cud use the following simple tcl
construct

if { [exa flg_addr_sent] == "1"} {
force -freeze data "0010101000010110"
}
where 'flg_addr_sent' is a signal which is turned high whenever the
address bits are sent and it is then turned low in the next clock
cycle. The 'data' signal is the signal which goes in to the input of
the entity which needs the pixel data.

for the purpose of testing only, i want a fixed data vector
("0010101000010110") to be sent to the screen.

However, when i use the do file and then simulate the test bench
containing all the component instantiations,
the data signal is never even changed...what could be going wrong
here?

To make it more clear, i type "vsim -d do-sim.do counters_TB.vhd"
and then all the requested signals are added
then i run it for 5us...but the signal 'data' didnt seemed to get
updated when the "flg_addr_sent" signal went high as can be seen from
the following screenshot i took :
http://picasaweb.google.com/aijazbaig1/WorkStuff/photo#5066235818306520466

id like to know if i cud modify something to give the correct stimulus
on the data signal when the flg_addr_sent signal is high?

hope to get some pointers from you,

regards,
Aijaz_

 

[Guy_Sweden]

Hello there.
I am trying to simulate the vga interface wherein the data (pixel
information) is read and formatted and then put on the screen in order
to reproduce the picture which is stored in the form of consecutive
pixels in a SRAM.

one of the modules in the interface sends the address to the SRAM
which then sends it the data (pixel) at that mem location. And certain
operations are to be help until we have received the pixl from the
SRAM. Theres one module which then receives the data from the SRAM and
then reformats it before sending it to the electron RGB guns which
then generate the color according to the information in that data.

Now before burning it to an actual FPGA, i wanna test if all the
timing criteria are being met elsewhere.

So when the module (entity) sends the address to be sent out to the
SRAM, i want to generate a 16 bit vector in response and send that to
the input of the entity which expects the data on the input.
In order to do that i thought i cud use the following simple tcl
construct

if { [exa flg_addr_sent] == "1"} {
force -freeze data "0010101000010110"}

where 'flg_addr_sent' is a signal which is turned high whenever the
address bits are sent and it is then turned low in the next clock
cycle. The 'data' signal is the signal which goes in to the input of
the entity which needs the pixel data.

for the purpose of testing only, i want a fixed color corresponding to the data vector
("0010101000010110") to be sent to the screen.

However, when i use the do file and then simulate the test bench
containing all the component instantiations,
the data signal is never even changed...what could be going wrong
here?

To make it more clear, i type "vsim -d do-sim.do counters_TB.vhd"
and then all the requested signals are added
then i run it for 5us...but the signal 'data' didnt seemed to get
updated when the "flg_addr_sent" signal went high as can be seen from
the following screenshot i took :http://picasaweb.google.com/aijazbaig1/WorkStuff/photo#50662358183065...
in that pic, one can see that counters_tb/flg_addr_sent goes however /counters_TB/data signal
remains at 'U' level. This is what im talkin about.
id like to know if i cud modify something to give the correct stimulus
on the data signal when the flg_addr_sent signal is high?

hope to get some pointers from you,

regards,
Aijaz_

 

[Duane Clark]

...
So when the module (entity) sends the address to be sent out to the
SRAM, i want to generate a 16 bit vector in response and send that to
the input of the entity which expects the data on the input.
In order to do that i thought i cud use the following simple tcl
construct

if { [exa flg_addr_sent] == "1"} {
force -freeze data "0010101000010110"
}

You really should not be using do files to generate stimulus (I have not
used one in something like a decade). You should create a simple top
level testbench file for this. For more complicated tests, you probably
want to create a separate file which generates the test stimulus and
checks results, and instantiate it into this top level (replacing the
data_p process). Since this is intended to control an SRAM, you probably
also should obtain a HDL model of the SRAM and instantiate that here too
(I'm guessing "data" is really the output of the RAM?).

entity bd_top is
end entity bd_top;

architecture board of bd_top is

constant CLK_PRD : Time := 10 nS;
signal CLK : std_logic;
signal flg_addr_sent : std_logic;
signal data : std_logic_vector(15 downto 0);

begin
UUT : entity work.vga
port map (
Clk => CLK,
flg_addr_sent => flg_addr_sent,
data => data
);

data_p: process(CLK)
begin
if rising_edge(CLK) then
if flg_addr_sent = '1' then
data <= X"2A16";
end if;
end if;
end process data_p;

-- Generate the clock.
clk_gen: process
begin
loop
Clk <= '1' after CLK_PRD/2, '0' after CLK_PRD;
wait for CLK_PRD;
end loop;
end process clk_gen ;

end architecture board;

 

[Chris Shenton]

You should be writing a testbench to do this type of thing. You will
find it much easier to model complex behaviour using VHDL or Verilog
rather than using do files.

Cheers

Chris