generated clocks

Discussion in 'VHDL' started by vic marks, Sep 2, 2006.

  1. vic marks

    vic marks Guest

    Hi,

    I need a suggestion in handling the generated clocks for synthesis, and DFT.
    What kind of constraints would be used for generated-clocks during
    synthesis, and DFT design.

    Thanking you for help.

    Best regards,
    vic
    vic marks, Sep 2, 2006
    #1
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  2. vic marks

    KJ Guest

    "vic marks" <> wrote in message
    news:63881$44f9bf51$50392791$...
    > Hi,
    >
    > I need a suggestion in handling the generated clocks for synthesis, and
    > DFT.
    > What kind of constraints would be used for generated-clocks during
    > synthesis, and DFT design.
    >

    Same constraints as with any other clock signal; namely, setup time and hold
    time for inputs, clock to output for outputs

    KJ
    KJ, Sep 2, 2006
    #2
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  3. vic marks

    arant Guest

    If you are usinng DCyou can use the create_generated_clock constraint
    Check out DC's man pages about usimg this command

    KJ wrote:
    > "vic marks" <> wrote in message
    > news:63881$44f9bf51$50392791$...
    > > Hi,
    > >
    > > I need a suggestion in handling the generated clocks for synthesis, and
    > > DFT.
    > > What kind of constraints would be used for generated-clocks during
    > > synthesis, and DFT design.
    > >

    > Same constraints as with any other clock signal; namely, setup time and hold
    > time for inputs, clock to output for outputs
    >
    > KJ
    arant, Sep 3, 2006
    #3
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