Generic design using generate statement

Discussion in 'VHDL' started by junaid.ece@gmail.com, Jan 15, 2006.

  1. Guest

    Hi,

    I want to have a very high generic model. For that I instantiate no. of
    modules in a generic way. And I need generic number of interconnecting
    to make connection between these modules..

    So Can I make the declaration in generic way using generate statement.?
    To be specific, can I use generate statement for declaration of
    variables..?

    Please relpy me...

    Junaid
    , Jan 15, 2006
    #1
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  2. wrote:

    > So Can I make the declaration in generic way using generate statement.?
    > To be specific, can I use generate statement for declaration of
    > variables..?


    Variables are declared inside the process,
    but variable types can use generic constants
    for any dimension of the structure.

    See the how the generic char_len_c
    is used in the reference design here:

    http://home.comcast.net/~mike_treseler/

    -- Mike Treseler
    Mike Treseler, Jan 15, 2006
    #2
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  3. Guest

    Mike Treseler wrote:
    > wrote:
    >
    > > So Can I make the declaration in generic way using generate statement.?
    > > To be specific, can I use generate statement for declaration of
    > > variables..?

    >
    > Variables are declared inside the process,
    > but variable types can use generic constants
    > for any dimension of the structure.
    >
    > See the how the generic char_len_c
    > is used in the reference design here:
    >
    > http://home.comcast.net/~mike_treseler/
    >
    > -- Mike Treseler


    Hi Mike,

    Thank you for your reply.

    I am basically dealing with SystemVerilog and want to have generic
    interconnecting wires..

    --Junaid
    , Jan 16, 2006
    #3
  4. Rob Dekker Guest

    <> wrote in message news:...
    >
    > Mike Treseler wrote:
    >> wrote:
    >>
    >> > So Can I make the declaration in generic way using generate statement.?
    >> > To be specific, can I use generate statement for declaration of
    >> > variables..?

    >>
    >> Variables are declared inside the process,
    >> but variable types can use generic constants
    >> for any dimension of the structure.
    >>
    >> See the how the generic char_len_c
    >> is used in the reference design here:
    >>
    >> http://home.comcast.net/~mike_treseler/
    >>
    >> -- Mike Treseler

    >
    > Hi Mike,
    >
    > Thank you for your reply.
    >
    > I am basically dealing with SystemVerilog and want to have generic
    > interconnecting wires..


    If you need help with System Verilog, try comp.lang.verilog.

    If you need to turn System Verilog into a VHDL design, then
    'generate' statements in SV work pretty similar to VHDL generate statements.

    You 'generate' concurrent statements, which means you can declare 'signals'
    and processes (with variables) under a generate statement.

    Rob

    >
    > --Junaid
    >
    Rob Dekker, Jan 16, 2006
    #4
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