Generic for Synthesis in Synplicity

Discussion in 'VHDL' started by bruceb58, Jan 11, 2010.

  1. bruceb58

    bruceb58

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    Jan 11, 2010
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    I would like to set a generic in a submodule to enable certain logic depending on the version of chip I am building. Is it required to route the generic all the way up to the top level to set it during synthesis or can it be done by specifying a path to the highest level that the generic exists in the Synplicity .prj file?
     
    bruceb58, Jan 11, 2010
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