generic map problem

Discussion in 'VHDL' started by pinky, Feb 9, 2009.

  1. pinky

    pinky

    Joined:
    Jan 28, 2009
    Messages:
    1
    Hi everyone,
    I am having a strange problem with making my code generic.
    I'll try to explain this complex problem as good as possible. I am coding the
    protocols between an SDRAM controller and a number of clients

    part of my code looks like this:
    when "100101111" => clientcyc(0) <= "0000";
    when "100110000" => clientcyc(1) <= "0001";
    when "100110001" => clientcyc(2) <= "0010";

    where clientcyc is a register which stores the number assigned to each client in each of it's array elements. Each client can communicate with a fifo in the RAM-controller which is done by mapping through a multiplexer.
    For the multiplexer the control input is the number assigned to each client.
    for eg, i looks like
    multiplexer_2 : process (clk)
    begin
    if rising_edge(clk)then
    port_sig <= clientcyc (x)
    case port_sig is

    when "0001" => tx_empty <= wr_fifo_empty(0);
    wr_fifo_rd_en(0) <= tx_ren;
    DI_tx <= wr_fifo_dout(0);
    rd_fifo_rd_en (0) <= rx_ren;
    rx_empty <= rd_fifo_empty(0);
    rx_full <= rd_fifo_full(0);
    data_rdy(0) <= di_ready;

    when "0010" => tx_empty <= wr_fifo_empty(1);
    wr_fifo_rd_en(1) <= tx_ren;
    DI_tx <= wr_fifo_dout(1);
    rd_fifo_rd_en (1) <= rx_ren;
    rx_empty <= rd_fifo_empty(1);
    rx_full <= rd_fifo_full(1);
    data_rdy(1) <= di_ready;

    so for each client number(for eg case "0001" corresponds to a client and "0010" to another) tx_ren ,rx_ren , rx_empty,rx_full etc. signals are mapped to the inputs and outputs of a fifo. The problem with this mapping technique
    is I cannot make it generic for any number of clients. Is there any method by which such mapping client and fifos can be done in a generic way. The fifos are generated in Xilinx ISE using the generate statement which is like this

    for i in 0 to (gClients - 1) generate
    tx_fifo : wr_fifo
    port map (
    din => DI_in(((i+1)*17-1) downto i*17),
    rd_clk => clk_a,
    rd_en => wr_fifo_rd_en(i),
    rst => rst,
    wr_clk => clk,
    wr_en => wr_en(i),
    dout => wr_fifo_dout(i),
    empty => wr_fifo_empty(i),
    full => wr_fifo_full(i));
    end generate;


    where gClients is the number of clients.

    Any kind of suggestions would be beneficial. And if somebody has any further queries please ask me
     
    pinky, Feb 9, 2009
    #1
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