Generic multiplexer

Discussion in 'VHDL' started by VladimirMatvejev@gmail.com, Oct 2, 2007.

  1. Guest

    Hello everybody,
    I want to make generic multiplexer. I am using FOR/GENERATE to make
    multiple code lines and conditional generate to make last line
    (without ELSE). Please, suggest what to do and why my code doesn't
    work. Thank you in advance.
    ----------------------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity gen_mux1 is
    generic(n: integer:=3);
    port (input : in std_logic_vector(2**n-1 downto 0);
    sell : in std_logic_vector(n-1 downto 0);
    output: out std_logic);
    end gen_mux1;

    architecture Behavioral of gen_mux1 is
    begin

    a: FOR i IN 0 TO 2**n-1 GENERATE
    b1: IF i /= 2**n-1 GENERATE
    output <= input(i) WHEN i = conv_integer(sel) ELSE
    END GENERATE;
    b2: IF i = 2**n-1 GENERATE
    output <= input(i) WHEN OTHERS
    END GENERATE;
    END GENERATE;
    end Behavioral;
    -----------------------------------------------------------------------------------------------------------------
    P.S. I want code to be concurrent.
    , Oct 2, 2007
    #1
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  2. Andy Guest

    Use ieee.numeric_std instead of std_logic_[arith, unsigned].

    Multiple concurrent assignments to the same signal (created by the
    generate loop) create multiple drivers for that signal. Your attempt
    could be modified to create a tristate mux (bus), but that is probably
    not what you want either:

    output <= input(i) when i = to_integer(unsigned(sel)) else 'Z';

    Not sure what you're trying to do with 2nd If-generate...

    You don't need the generate statements (loop or if) anyway:

    -- since sel is constrained to be within input'range:
    use ieee.numeric_std.all;
    architecture concurrent of gen_mux1 is
    begin
    output <= input(to_integer(unsigned(sel)));
    end architecture;

    -- or this will work if value of sel could be
    -- outside of input'range:
    use ieee.numeric_std.all;
    architecture sequential of gen_mux1 is
    begin
    process (input, sel) is
    begin
    output <= '0'; -- default assignment
    for i in input'range loop
    if i = to_integer(unsigned(sel)) then
    output <= input(i);
    end if;
    end loop;
    end process;
    end architecture;

    Andy
    Andy, Oct 2, 2007
    #2
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