Generic Multiplexer

Discussion in 'VHDL' started by Vinny P, Sep 18, 2009.

  1. Vinny P

    Vinny P

    Joined:
    Sep 18, 2009
    Messages:
    3
    Hi,

    I am trying to create a N input mux and an N output Demux but the Xilinx Xst does not show a multiplexer in the synthesis report. In the code below the attempt for these hardware units are shown in process MUXes_FOR_PORT_A, DeMUXes_FOR_PORT_A, MUXes_FOR_PORT_B and DeMUXes_FOR_PORT_B. Can anyone guide me in producing N input mux and an N output Demux that is recognized by the XST synthesis tool.

    Code:
    h++p://pastebin.com/f71b18f73
    
    Thank you in Advance,
    Vinny P
     
    Vinny P, Sep 18, 2009
    #1
    1. Advertising

  2. Vinny P

    Vinny P

    Joined:
    Sep 18, 2009
    Messages:
    3
    Pop-up! :)

    Still can't figure this out :oops:

    Thank you,
    Vince
     
    Vinny P, Sep 22, 2009
    #2
    1. Advertising

  3. Vinny P

    StuartHobday

    Joined:
    Sep 22, 2009
    Messages:
    7
    Location:
    Dorset
    This syntax will create a N-input mux:

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;

    ENTITY NInputMux IS

    GENERIC( MuxSize : INTEGER := 4
    );
    PORT( InputBusSelect : IN std_logic;
    InputBusA : IN std_logic_vector((MuxSize-1) DOWNTO 0);
    InputBusB : IN std_logic_vector((MuxSize-1) DOWNTO 0);
    OutputBus : OUT std_logic_vector((MuxSize-1) DOWNTO 0)
    );
    END NInputMux;


    ARCHITECTURE Behavioural OF NInputMux IS

    CONSTANT BusA : std_logic := '1';

    BEGIN

    OutputBus<= InputBusA WHEN ( InputBusSelect = BusA
    )
    ELSE InputBusB;

    END;

    The construct in your design will use combinatorial logic rather than muxes as you are only assigning zero's to the output bus. The above example should help you design the demux.
     
    StuartHobday, Sep 22, 2009
    #3
  4. Vinny P

    Vinny P

    Joined:
    Sep 18, 2009
    Messages:
    3
    StuartHobday,

    Thank you for your reply. I may not have been clear on the first post, I am trying to make a N to 1 mux and a 1 to N demux. The code you have posted is a mux structure with a variable length input. I am trying to vary the number of input to a mux and the number of outputs to a demux.

    Looking forward to your reply.

    Thank you,
    Vinny P
     
    Vinny P, Sep 24, 2009
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Lily
    Replies:
    6
    Views:
    4,760
    Eric Smith
    Apr 29, 2004
  2. bxbxb3

    Big multiplexer?

    bxbxb3, Apr 15, 2005, in forum: VHDL
    Replies:
    5
    Views:
    800
    bxbxb3
    Apr 19, 2005
  3. woko

    Multiplexer Index

    woko, Aug 3, 2005, in forum: VHDL
    Replies:
    2
    Views:
    573
  4. Weng Tianxiang
    Replies:
    12
    Views:
    1,709
  5. VladimirMatvejev@gmail.com

    Generic multiplexer

    VladimirMatvejev@gmail.com, Oct 2, 2007, in forum: VHDL
    Replies:
    1
    Views:
    652
Loading...

Share This Page