Generic Multiplexer

[Vinny P]

Hi,

I am trying to create a N input mux and an N output Demux but the Xilinx Xst does not show a multiplexer in the synthesis report. In the code below the attempt for these hardware units are shown in process MUXes_FOR_PORT_A, DeMUXes_FOR_PORT_A, MUXes_FOR_PORT_B and DeMUXes_FOR_PORT_B. Can anyone guide me in producing N input mux and an N output Demux that is recognized by the XST synthesis tool.

h++p://pastebin.com/f71b18f73

Thank you in Advance,
Vinny P

 

[Vinny P]

Pop-up!

Still can't figure this out

Thank you,
Vince

 

[StuartHobday]

This syntax will create a N-input mux:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY NInputMux IS

GENERIC( MuxSize : INTEGER := 4
);
PORT( InputBusSelect : IN std_logic;
InputBusA : IN std_logic_vector((MuxSize-1) DOWNTO 0);
InputBusB : IN std_logic_vector((MuxSize-1) DOWNTO 0);
OutputBus : OUT std_logic_vector((MuxSize-1) DOWNTO 0)
);
END NInputMux;


ARCHITECTURE Behavioural OF NInputMux IS

CONSTANT BusA : std_logic := '1';

BEGIN

OutputBus<= InputBusA WHEN ( InputBusSelect = BusA
)
ELSE InputBusB;

END;

The construct in your design will use combinatorial logic rather than muxes as you are only assigning zero's to the output bus. The above example should help you design the demux.

 

[Vinny P]

StuartHobday,

Thank you for your reply. I may not have been clear on the first post, I am trying to make a N to 1 mux and a 1 to N demux. The code you have posted is a mux structure with a variable length input. I am trying to vary the number of input to a mux and the number of outputs to a demux.

Looking forward to your reply.

Thank you,
Vinny P