I have a component which has a latency that needs to be known by
anything that instantiates it. The component sits in its own library
and so I've created a package with the latency in that is included by
anything that instantiates the component. Is that the good way of
doing things?
Sounds OK to me. Keep related stuff together, as always. You could
put the component definition in the same package, if you don't mind
using indirect (component) instantiation.
Now, I want to have two different versions of the component,
controlled by a generic. Unfortunately the latency of the component
will be different for each version. How can I go about providing the
latency as a constant now? As I understand it, you can't have generics
in a package.
Fascinating. Almost exactly this was raised by someone else only
a couple of months ago, and it generated quite heated debate.
To set the record straight: VHDL does *not* provide any decent
way to propagate constant values UP the design hierarchy.
Generics, as I'm sure you've worked out for yourself, are
intended to propagate information DOWN the hierarchy, from
parent module to embedded instance.
Now, I want to have two different versions of the component,
controlled by a generic. Unfortunately the latency of the component
will be different for each version. How can I go about providing the
latency as a constant now?
When you say "controlled by a generic", do you mean that a
generic of the upper, instantiating module will control which
version is instantiated, using "if generate" or somesuch?
Or do you mean that you supply a generic to the component,
and as a consequence of that generic value its latency
can take one of two possible values? If it's the latter,
then I would have thought you could put a function into
your package that would return the latency as a function
of the generic (by table lookup or whatever). Or provide
a table of constants in the package, yielding latency as
a function of some enumeration type (which you could later
extend); you could then use the same enumeration type to
specify which version of the module you wish to instance.
As I understand it, you can't have generics in a package.
Correct, although VHDL-200x will offer package generics
which probably will do something like what you require.
You may need to beat on your tool vendor to get support
for package generics, though.
I suppose an alternative is to create a integer port on the component
which outputs the latency, but that's really horrible. Is there any
better of doing what I've described?
I'm not sure I understand what's so horrible about it.
Presumably the device must in some way inform the enclosing
module about its behaviour; why not by exposing some constant
value through a port? Synthesis should do The Right Thing (tm)
with it.
Otherwise, I'm afraid, it's a matter of finding *some* way
to drive the hierarchy from above, not from below.
Upwards propagation of generics (or parameters, or constants,
or whatever you like to call them) is a sure way to get nasty
problems with circular references at elaboration. For an
entertaining case in point, take a look at the way the Verilog
standard has had to be tweaked to avoid exactly these cyclic
parameter specification issues, since Verilog does indeed
offer arbitrary propagation of parameters up and down the
hierarchy using its "defparam" feature.
--
Jonathan Bromley, Consultant
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