Generics and state machines

Discussion in 'VHDL' started by Steve, May 3, 2004.

  1. Steve

    Steve Guest

    Hi, I would like to create a state machine that is of generic size.
    It is for accessing offchip memory, having parallel components attempting to
    access and delivering access to one at a time. I just don't know how many
    different components are trying to access the memory until I use it.

    is there a way to create state type of arrays, so that generics can be used
    to create the size
    of the state machine???

    steve
    Steve, May 3, 2004
    #1
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  2. Steve

    Jim Lewis Guest

    Steve,
    Draw a picture and partition your design first.
    Start with a fixed number of elements and then
    figure out how to apply generics (and where they
    are appropriate).

    You have N devices. Each must manage its own
    address and data. Each must handshake with
    the Memory Controller in turn. Each will only
    read or write data when it is selected.

    You have something to choose one of the N devices:
    An arbiter.

    You have a multiplexer to route address and data
    from the active device to the memory.

    You have one memory controller. It probably
    does not need to know that there is more than
    one device connected to it.

    With this view, only the Arbiter
    and the Memory multiplexer will have generics.
    The arbiter will have request and grant signals.
    The memory multiplexer will need to handle
    N address and data busses.

    This should give you a start.

    Cheers,
    Jim


    > Hi, I would like to create a state machine that is of generic size.
    > It is for accessing offchip memory, having parallel components attempting to
    > access and delivering access to one at a time. I just don't know how many
    > different components are trying to access the memory until I use it.
    >
    > is there a way to create state type of arrays, so that generics can be used
    > to create the size
    > of the state machine???
    >
    > steve


    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis, May 3, 2004
    #2
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  3. Steve

    Tom Hawkins Guest

    "Steve" <> wrote in message news:<ppklc.26898$>...
    > Hi, I would like to create a state machine that is of generic size.
    > It is for accessing offchip memory, having parallel components attempting to
    > access and delivering access to one at a time. I just don't know how many
    > different components are trying to access the memory until I use it.
    >
    > is there a way to create state type of arrays, so that generics can be used
    > to create the size
    > of the state machine???
    >
    > steve


    If the machine is farily simple, you might be able to use GENERATE to
    extend it's functionality, i.e. increase its size. But I suspect
    there may not be a clean solution with VHDL.

    This sort of task is a snap with Conflunce. Just write an algorithm
    to build the state transition table, then instantiate a state machine
    with the given table. At a higher level of abstract, you could simply
    pass in a list of component interface, then generate the logic for
    each. The length of the interface list acts as a configuration
    parameter.

    -Tom
    Tom Hawkins, May 3, 2004
    #3
  4. Steve

    Jim Lewis Guest

    Tom Hawkins wrote:
    > "Steve" <> wrote in message news:<ppklc.26898$>...
    >
    >>Hi, I would like to create a state machine that is of generic size.
    >>It is for accessing offchip memory, having parallel components attempting to
    >>access and delivering access to one at a time. I just don't know how many
    >>different components are trying to access the memory until I use it.
    >>
    >>is there a way to create state type of arrays, so that generics can be used
    >>to create the size
    >>of the state machine???
    >>
    >>steve

    >
    >
    > If the machine is farily simple, you might be able to use GENERATE to
    > extend it's functionality, i.e. increase its size. But I suspect
    > there may not be a clean solution with VHDL.
    >
    > This sort of task is a snap with Conflunce. Just write an algorithm
    > to build the state transition table, then instantiate a state machine
    > with the given table. At a higher level of abstract, you could simply
    > pass in a list of component interface, then generate the logic for
    > each. The length of the interface list acts as a configuration
    > parameter.
    >


    Gee Tom, that looks like a shameless marketing plug for your product.
    Does confluence allow you to forget about hardware?
    That seems to be the main issue here. Once you sort
    out what hardware you care to implement, it is
    clean and easy with VHDL.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis, May 4, 2004
    #4
  5. Steve

    Tom Hawkins Guest

    Jim Lewis <> wrote in message news:<>...
    > Tom Hawkins wrote:
    > > "Steve" <> wrote in message news:<ppklc.26898$>...
    > >
    > >>Hi, I would like to create a state machine that is of generic size.
    > >>It is for accessing offchip memory, having parallel components attempting to
    > >>access and delivering access to one at a time. I just don't know how many
    > >>different components are trying to access the memory until I use it.
    > >>
    > >>is there a way to create state type of arrays, so that generics can be used
    > >>to create the size
    > >>of the state machine???
    > >>
    > >>steve

    > >
    > >
    > > If the machine is farily simple, you might be able to use GENERATE to
    > > extend it's functionality, i.e. increase its size. But I suspect
    > > there may not be a clean solution with VHDL.
    > >
    > > This sort of task is a snap with Conflunce. Just write an algorithm
    > > to build the state transition table, then instantiate a state machine
    > > with the given table. At a higher level of abstract, you could simply
    > > pass in a list of component interface, then generate the logic for
    > > each. The length of the interface list acts as a configuration
    > > parameter.
    > >

    >
    > Gee Tom, that looks like a shameless marketing plug for your product.


    Yes, it was a shameless plug for a tool that is open-source (GPL).
    Here's another one: http://www.launchbird.com/


    > Does confluence allow you to forget about hardware?


    No. On the contrary, Confluence forces you to take an even closer
    look at your hardware structures and the algorithms that generate
    them.

    The key is the fundamental paradigm shift between HDL and Confluence:
    An HDL design describes a single structure, where as a Confluence
    design is an algorithm to generate an entire class of structures.

    > That seems to be the main issue here. Once you sort
    > out what hardware you care to implement, it is
    > clean and easy with VHDL.


    This is true assuming you know the hardware you need to implement.
    But here in lies the problem. As Steve clearly states, "I just don't
    know how many different components are trying to access the memory
    until I use it."

    Confluence solves this problem by providing more mechanisms for reuse.
    Users can design the generic case up front, then instantiate a
    specific configuration once the requirements have solidified.

    -Tom

    >
    > Cheers,
    > Jim
    > --
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    > Jim Lewis
    > Director of Training mailto:
    > SynthWorks Design Inc. http://www.SynthWorks.com
    > 1-503-590-4787
    >
    > Expert VHDL Training for Hardware Design and Verification


    Jim, your tag-line should read:

    Expert Confluence and VHDL Training for Hardware Design and
    Verification

    ;-)

    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Tom Hawkins, May 4, 2004
    #5
  6. Steve

    Jim Lewis Guest

    Tom,
    > No. On the contrary, Confluence forces you to take an even closer
    > look at your hardware structures and the algorithms that generate
    > them.

    I am glad to see we agree that you can't forget about
    the hardware. When one forgets about the hardware, they
    get what they deserve.

    Once we figure out the nature of the hardware and what to
    do for a fixed number of iterations it is fairly straight
    forward to genericize it with VHDL.

    The problematic places of this problem are the arbiter (select
    active device) and the memory multiplexer (select address and
    data to memory for the active device).

    The arbiter has request and grant signals. Each of these can
    use generics an array with the width that matches the number
    of devices in the system. The width would be specified by
    a generic.

    The memory multiplexer is a little more tricky as the objects
    that need to be multiplexed are the address and data busses.
    We need a couple of types defined to be an unconstrained
    array of an array type. One to hold address and one to hold
    data.

    At this point I think I have done enough of the homework
    problem that was posted.

    This is not just theoretically do-able in VHDL, I have done it.
    It is not difficult, you just need to be organized and
    structure the problem right (as you would have to do for any
    solution - even confluence).


    > Expert Confluence and VHDL Training for Hardware Design and
    > Verification

    Hart to tell. I am a strong typing fan. I don't like
    debugging in the simulator - I prefer to debug in the
    compiler.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis, May 5, 2004
    #6
  7. Steve

    Tom Hawkins Guest

    Jim Lewis <> wrote in message

    [snip]

    >
    >
    > > Expert Confluence and VHDL Training for Hardware Design and
    > > Verification

    > Hart to tell. I am a strong typing fan. I don't like
    > debugging in the simulator - I prefer to debug in the
    > compiler.


    I agree completely. Static typing is an incredibly powerful, yet
    often undervalued method for uncovering bugs. I wouldn't have been
    able to get Confluence to where it is today without the static type
    system of Objective Caml.

    Confluence is a dynamically typed language from the software
    standpoint. However, in light of the "generate" paradigm, running a
    Confluence program to produce a netlist is still part of the
    compilation process. Since the run-time environment handles type
    checking, and the run-time is part of the netlist compilation,
    Confluence can be considered a staticly typed language.

    In other words, if you can successfully compile a Confluence program
    to a netlist, you have strict guarantees of the resulting netlist
    quality.


    -Tom

    >
    > Cheers,
    > Jim
    > --
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    > Jim Lewis
    > Director of Training mailto:
    > SynthWorks Design Inc. http://www.SynthWorks.com
    > 1-503-590-4787
    >
    > Expert VHDL Training for Hardware Design and Verification
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Tom Hawkins, May 5, 2004
    #7
  8. Hi,

    Tom Hawkins wrote:

    >
    > I agree completely. Static typing is an incredibly powerful, yet
    > often undervalued method for uncovering bugs. I wouldn't have been
    > able to get Confluence to where it is today without the static type
    > system of Objective Caml.
    >

    Yes, but in OCaml typing is very convinient due to type interference
    and polymorph functions. Doing the same hack in i.e. C++ will probably
    drive you crazy.

    And i assume that Confluence would not be where it is without the other
    nice features that OCaml brings to you ;-)

    However, from my experience bugs from odd typing are not very hard to catch.
    Much more ugly are "dynamic" bugs, i.e. a wrong assumption about any system
    constraint (typical "This will never happen"). To get rid of these i like to
    have a bunch of monitors and condition handlers in my code that tries to fix
    it or, at least, halts the program gracefully (i.e. saving the data and write
    a stack trace).

    Just my $0.01 ;-)

    Kind regards
    AHz
    Andreas Hinze, May 5, 2004
    #8
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