generics in type definition?

Discussion in 'VHDL' started by MM, Aug 17, 2006.

  1. MM

    MM Guest

    Hi,

    I have the following type and I want to be able to have different RdCount
    and WrCount widths for different FIFOs without declaring a new type every
    time. How can I do it in VHDL?

    type FIFO_FLAGS_TYPE is record
    Full : std_logic;
    Empty : std_logic;
    AlmostFull : std_logic;
    AlmostEmpty : std_logic;
    Underflow : std_logic;
    Overflow : std_logic;
    RdCount : std_logic_vector(8 downto 0);
    WrCount : std_logic_vector(8 downto 0);
    end record FIFO_FLAGS_TYPE;

    Thanks,
    /Mikhail
     
    MM, Aug 17, 2006
    #1
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  2. MM

    Andy Guest

    Assuming you want this to be synthesizable, you can't really do it...

    But there are some ways you can set it up such that you never need to
    change it...

    1. Declare the vectors as the longest you would ever need, but when
    they break out to individual signals, only hook up the bits you really
    need. This can get a little verbose, but things like
    numeric_std.resize() work well (BTW, I would make those unsigned
    instead of SLV).

    2. For counts up to 2**31 - 1, declare those elements of the record as
    natural. Then hook them up to smaller natural subtypes as you break
    them out. Integers work better for counters anyway. Much less verbocity
    in hooking stuff up than with vectors (unsigned or SLV). This would be
    my preferred choice.

    Both of these methods will result in the synthesis tool optimizing out
    the unused (unconnected) bits.

    Sometimes it is easier to define things that you know the tools will
    optimize away, than to code it exactly anyway.

    If this is only for simulation, use access types for the counts.

    Andy


    MM wrote:
    > Hi,
    >
    > I have the following type and I want to be able to have different RdCount
    > and WrCount widths for different FIFOs without declaring a new type every
    > time. How can I do it in VHDL?
    >
    > type FIFO_FLAGS_TYPE is record
    > Full : std_logic;
    > Empty : std_logic;
    > AlmostFull : std_logic;
    > AlmostEmpty : std_logic;
    > Underflow : std_logic;
    > Overflow : std_logic;
    > RdCount : std_logic_vector(8 downto 0);
    > WrCount : std_logic_vector(8 downto 0);
    > end record FIFO_FLAGS_TYPE;
    >
    > Thanks,
    > /Mikhail
     
    Andy, Aug 17, 2006
    #2
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  3. MM

    MM Guest

    Thanks Andy. The reason I chose SLV was because the FIFOs I am hooking this
    up to have their ports defined as SLV (they are Xilinx Coregen generated)...

    /Mikhail
     
    MM, Aug 17, 2006
    #3
  4. MM

    Charles, NG Guest

    Hello Mikhail,

    something like the following should work. It should even be synthesisable.

    Library IEEE;
    Use IEEE.std_logic_1164.all;
    Use IEEE.numeric_std.all;

    Entity asdf is
    Generic (
    g_WordSize : integer := 8;
    g_WS2 : integer := 15
    );
    Port (
    i_din : in std_logic_vector(15 downto 0);
    o_dout : out std_logic_vector(g_WS2 - 1 downto 0)
    );
    End asdf;

    Architecture Bhv of asdf is
    type t_asdf is record
    f1 : std_logic_vector(g_WordSize - 1 downto 0);
    f2 : std_logic_vector(i_din'range);
    f3 : std_logic_vector(o_dout'range);
    end record;
    Begin
    o_dout <= std_logic_vector(resize(unsigned(i_din), o_dout'length));
    End Bhv;

    Hope this helps,
    Charles
     
    Charles, NG, Aug 18, 2006
    #4
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