Get the carry with add operator

[Damien Bardon]

Hello,

I would like to add two 4 bits number, and get the result and the carry. Is
there any way too do that with the '+' operator ? Otherwise, what is the
best way to solve this problem ?

Thank you I search a lot without any success.

Damien_

 

[Mike Treseler]

I would like to add two 4 bits number, and get the result and the carry. Is
there any way too do that with the '+' operator ?

http://groups.google.com/groups/search?q=vhdl+unsigned_carry

 

[Eric Smith]

I would like to add two 4 bits number, and get the result and the carry. Is
there any way too do that with the '+' operator ? Otherwise, what is the
best way to solve this problem ?

If you concatenate a "0" on the front of each number, then add them,
the low four bits of the result are your sum, and the high bit is
the carry out.

Example below; I haven't actually compiled this exact code, but it's
basically a simplified version of something I actually use.

If you also want a signed arithmetic overflow output (which is NOT the
same thing as carry out), you can get that by using a two bit extension
rather than a single bit.

Lately I've been having fun with BCD/binary adder/subtractors, using
carry select and carry lookahead. With careful desgin (but FPGA vendor
neutral and not floorplanned), I was able to get a 56 bit version with
minimum cycle time of just over 10 ns.

Eric


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity binary_adder_with_carry_out is
generic (width: integer := 4);
port (operand_a: in std_logic_vector (width - 1 downto 0);
operand_b: in std_logic_vector (width - 1 downto 0);
carry_in: in std_logic;
result: out std_logic_vector (width - 1 downto 0);
carry_out: out std_logic);
end binary_adder_with_carry_out;

architecture behavioral of binary_adder_with_carry_out is
signal a_ext: unsigned (width downto 0);
signal b_ext: unsigned (width downto 0);
signal c_ext: unsigned (0 downto 0);
signal temp: unsigned (width downto 0);
begin
a_ext <= unsigned ("0" & operand_a);
b_ext <= unsigned ("0" & operand_b);
c_ext (0) <= carry_in;

temp <= a_ext + b_ext + c_ext;

result <= temp (width - 1 downto 0);
carry_out <= temp (width);
end behavioral;

 

[Andy]

Using integer types, and subtypes thereof, you can do this:

signal a,b,sum : natural range 0 to 2**N-1; -- N-bit unsigned values
signal carry_out : natural range 0 to 1;
....
sum <= (a + b) mod 2**N;
carry_out <= ((a + b) / 2**N) mod 2;

Operations on all integer types/subtypes are 32 bits (31 bits unsigned)
wide, only the assignments are restricted to the range of the subtype,
which determines data widths of registers. The synthesis tool will
optimize out any unused bits.

Note that the / and mod operators are just shift/truncate in hardware,
and both will execute MUCH faster in simulation than vector types (SLV,
unsigned, etc.)

I only wish vhdl supported 64 and/or 128 bit integer types.

Andy

 

[Damien Bardon]

Thank you for your answers, I like Eric's solution, as Andy's proposal is
too complicated for me yet I hope I will understand such a solution in
a few time !

Actually I had already try something similar to Eric's solution but although
it was working, I was wondering if it is a good practice, as the
synthesizer generate a 5 bits adder instead of a 4 bits adder with carry
out.

Damien_

 

[Mike Treseler]

Actually I had already try something similar to Eric's solution but although
it was working, I was wondering if it is a good practice, as the
synthesizer generate a 5 bits adder instead of a 4 bits adder with carry
out.

Use that fifth bit as your carry out.
That's what the resize is for in my example.

Better yet, just use the full width
that you really need and don't describe
any carry.

-- Mike Treseler