ghdl unsigned

Discussion in 'VHDL' started by revu, Mar 1, 2008.

  1. revu

    revu Guest

    revu, Mar 1, 2008
    #1
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  2. revu

    KJ Guest

    "revu" <> wrote in message
    news:...
    >i tried writin a vhdl code for up/down counter in ghdl .. i cant add 2
    > std_logic_vectors using '+'sign.. i tried includ'g ieee.numeric_std.all..
    > but not wrking.. wat to do??
    >


    You need to convert the std_logic_vectors to unsigned (or perhaps signed,
    not sure what you want them to be). Std_logic_vectors by themselves have no
    sense of any numeric values, they are simply a collection of bits. The
    unsigned and signed data types are also a collection of bits but by using
    them you are saying that this collection of bits has a definite numeric
    interpretation and furthermore that collection is a signed 2 complement
    representation (signed) or simply an unsigned representation (unsigned).
    The 'conversion' of std_logic_vector to/from signed or unsigned costs
    nothing in synthesis so don't think you're chewing up resources by using
    them. The conversion is simply telling the compiler that you have a
    specific interpretation that you'd like to apply to this collection of bits.

    So, assuming A, B and C to all be std_logic_vectors of the appropriate width
    that all are to be interpreted as unsigned numbers, then to add A and B to
    produce C you would do the following

    use ieee.numeric_std.all; -- This package defines how '+' works with two
    unsigneds
    ....
    C <= std_logic_vector(unsigned(A) + unsigned(B));

    Kevin Jennings
    KJ, Mar 1, 2008
    #2
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  3. revu

    diogratia Guest

    revu wrote:
    > i tried writin a vhdl code for up/down counter in ghdl .. i cant add 2
    > std_logic_vectors using '+'sign.. i tried includ'g ieee.numeric_std.all..
    > but not wrking.. wat to do??
    >
    > --
    > Message posted using http://www.talkaboutprogramming.com/group/comp.lang.vhdl/
    > More information at http://www.talkaboutprogramming.com/faq.html


    Predefined Adding operators are only available for numeric types and
    are not defined in the IEEE package std_logic_1164. While you could
    define your own adding operator as a function, there are predefined
    operators that use subtype to distinguish between signed and unsigned
    numbers. These can be found in the IEEE numeric_std package. It
    might be contraindicated to use your own creative solution based on
    any anticipated synthesis. Ghdl has the numeric_std package already
    compiled and available.

    Using the additional types can require type conversion

    type_conversion ::= type_mark
    ( expression ) [§ 7.3.5]

    Explicit type conversions are allowed between closely related types.

    Two array types are closely related if and only if

    -- The types have the same dimensionality;

    -- For each index position, the index types are either the same
    or are closely related; and

    -- The element types are the same.


    type_mark ::=
    [§ 4.2]
    type__name
    | subtype__name

    The package declarations and package bodies as source are found in the
    gcc vhdl library included with the installation of ghdl.
    diogratia, Mar 3, 2008
    #3
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