revu said:
i tried writin a vhdl code for up/down counter in ghdl .. i cant add 2
std_logic_vectors using '+'sign.. i tried includ'g ieee.numeric_std.all..
but not wrking.. wat to do??
You need to convert the std_logic_vectors to unsigned (or perhaps signed,
not sure what you want them to be). Std_logic_vectors by themselves have no
sense of any numeric values, they are simply a collection of bits. The
unsigned and signed data types are also a collection of bits but by using
them you are saying that this collection of bits has a definite numeric
interpretation and furthermore that collection is a signed 2 complement
representation (signed) or simply an unsigned representation (unsigned).
The 'conversion' of std_logic_vector to/from signed or unsigned costs
nothing in synthesis so don't think you're chewing up resources by using
them. The conversion is simply telling the compiler that you have a
specific interpretation that you'd like to apply to this collection of bits.
So, assuming A, B and C to all be std_logic_vectors of the appropriate width
that all are to be interpreted as unsigned numbers, then to add A and B to
produce C you would do the following
use ieee.numeric_std.all; -- This package defines how '+' works with two
unsigneds
....
C <= std_logic_vector(unsigned(A) + unsigned(B));
Kevin Jennings