Hi everyone,
I’m trying to generalize the following code so that RST_cmp can have any number of bits (b) and the number of state_counter can also change (upperbound).
CODE in PROCESS:
if state_counter = 0 then
I want to generalize it so that if I have ‘b’ bits in RST_cmp it will automatically make the same if, elsif, else structure but scaled to not only how many ‘b’ bits there are but also scaled to whatever my max ‘state_counter’ is.
I wanted to use something like this but it does not seem to work under Xilinx ISE. Am I doing anything wrong?
if state_counter = 0 then
else
1) Would my generic code work with having a for statement in the middle of a if,elsif, else statement?
2) If not have would I do such a thing?
3) Is my idea of using a Generate statement valid in this context?
Thank you for your ideas,
Michael
I’m trying to generalize the following code so that RST_cmp can have any number of bits (b) and the number of state_counter can also change (upperbound).
CODE in PROCESS:
if state_counter = 0 then
RST_cmp(0) <= '0';
RST_cmp(1) <= '1';
Daddr <= Daddr + 1;
state_counter <= state_counter+1;
elsif state_counter = 1 thenRST_cmp(1) <= '1';
Daddr <= Daddr + 1;
state_counter <= state_counter+1;
RST_cmp(1) <= '0';
RST_cmp(2)<= '1';
state_counter <= state_counter+1;
elsif state_counter = 2 thenRST_cmp(2)<= '1';
state_counter <= state_counter+1;
RST_cmp(2)<= '0';
RST_cmp(3)<= '1';
state_counter <= state_counter+1;
elsif state_counter = 3 thenRST_cmp(3)<= '1';
state_counter <= state_counter+1;
RST_cmp(4) <=’0’;
state_counter <= state_counter+1;
elsif state_counter = 3 thenstate_counter <= state_counter+1;
state_counter <= state_counter+1;
else RST_cmp(0) <= '1';
Daddr <= Daddr + 1;
state_counter <= (others => '0');
end if;Daddr <= Daddr + 1;
state_counter <= (others => '0');
I want to generalize it so that if I have ‘b’ bits in RST_cmp it will automatically make the same if, elsif, else structure but scaled to not only how many ‘b’ bits there are but also scaled to whatever my max ‘state_counter’ is.
I wanted to use something like this but it does not seem to work under Xilinx ISE. Am I doing anything wrong?
if state_counter = 0 then
RST_cmp(0) <= '0';
RST_cmp(1) <= '1';
Daddr <= Daddr + 1;
state_counter <= state_counter+1;
for i in 1 to upperbound loopRST_cmp(1) <= '1';
Daddr <= Daddr + 1;
state_counter <= state_counter+1;
elsif state_counter = i then
GEN1: if i <= b generate
state_counter <= state_counter+1;
end loop;GEN1: if i <= b generate
RST_cmp(i) <= '0';
RST_cmp(i+1)<= '1';
end generate;RST_cmp(i+1)<= '1';
state_counter <= state_counter+1;
else
RST_cmp(0) <= '1';
Daddr <= Daddr + 1;
state_counter <= (others => '0');
end if;Daddr <= Daddr + 1;
state_counter <= (others => '0');
1) Would my generic code work with having a for statement in the middle of a if,elsif, else statement?
2) If not have would I do such a thing?
3) Is my idea of using a Generate statement valid in this context?
Thank you for your ideas,
Michael