Glitches?

[The Weiss Family]

All,

I'm pretty new to VHDL and FPGAs in general.
I have designed my system and simulated portions of it with ModelSim.
When I simulate the behavioral model, everything is great.
When I simulate the post place and route model, I get a bunch of warnings
indicating that the pulse width on a bunch of signals is less than some
expected value. I'm assuming this means that the signals are "glitching".
What causes this?
Is there something in particular in my code I can look for to correct this?

Thanks,

Adam

 

[Ralf Hildebrandt]

The Weiss Family wrote:

When I simulate the post place and route model, I get a bunch of warnings
indicating that the pulse width on a bunch of signals is less than some
expected value. I'm assuming this means that the signals are "glitching".
What causes this?
Is there something in particular in my code I can look for to correct this?

Look at the warnings. You will read a name of the device, that produces
the glitches (e.g. a flipflop) and the name of the device itself or at
least the names of the wires. Search for these names in you netlist
(synthesis output). Try to find out, what part of your design is meant.
(Every flipflop, latch or block of combinational logic is a "part".
Often a "part" is, what you have described in one process.)

The most important warnings a things like "setup time violation ... A
with respect to C" (data-in of a flipflop changes short before clock has
an edge). Here you have to modify your design, to make this not happen.

Sometimes a simulator may be configured to produce warnings for every
glitch - even in pure combination logic. Often this is useless, as
glitches in combinational logic are quite usual. Ask your "CAD-support"
how to turn off these warnings.


Ralf

 

[Mike Treseler]

When I simulate the post place and route model, I get a bunch of warnings
indicating that the pulse width on a bunch of signals is less than some
expected value. I'm assuming this means that the signals are "glitching".
What causes this?

Asynchronous logic.

Is there something in particular in my code I can look for to correct
this?

Consider using the synchronous template
http://groups.google.com/groups?q=vhdl+synchronous+template
for all vhdl processes.

-- Mike Treseler

 

[The Weiss Family]

All,

Thanks for the input. I actually figured it out in the shower this morning
(where I do my best thinking). You were right. It was due to asynchronous
logic. I will just synchronize my design, and my problems should go away!

I'm slowly beginning to think like an FPGA designer!

Thanks again,

Adam