Global Constants

[ed]

Hi,

I have some constants in my VHDL design, which I want to access from
different modules. Can I make the constants global? Or do I have to
redefine them in multiple modules?

Thanks.

 

[Jezwold]

You can make them global by defining them in a package 'mypackage' and
then
compile the package which will default be compiled into the work
library
use work.mypackage.all;
will make the constants visible.

 

[Jezwold]

Sorry that didn't come out very well,
What I mean ot say was once you have compiled your package it will by
default be compiled into the 'work' library.In all of your modules that
you wish to make the constants visible usa a
use work.mypackage.all;
and then all the package contents,including any constants, will be
visible in that module.

 

[Ralf Hildebrandt]

I have some constants in my VHDL design, which I want to access from
different modules. Can I make the constants global? Or do I have to
redefine them in multiple modules?

Jezworld has suggested to declare the constants in a package. An other
option is to use generic parameters.

entity myentity is
generic(
mygenericparam : integer:=1 );
port(
in : std_ulogic;
out : std_ulogic );

When instantiating an component, a constant can be "generic-mapped" to
the generic parameter and it will override the perameter.

Ralf