Sorry to everyone, I just found out what was the problem. Actually there
where severals:
1) unused registers where only due to the fact that not all the
registers included in my package where used. When I called the library
work I select "all" of the components, so I think this is the reason
(correct me if I am wrong)
2) Apparently is not possible to have a vector that is partially
assigned in one block and the partially in another. When it synthesizes
the register it will always miss a part of it, getting to the point that
at the very end the full register is never assigned completely.
Are these conclusions correct?
Al, I think you should ask your vendor (Synplify) if they actually support shared variables or global signals or not. Many commercial synthesizers do not actually support shared variables or (global) signals within a package body. What you can do is create a package with whatever components you want, then create a separate vhdl file with an entity-architecture structure to connect those components together. Then in that way, you can include the file (the one with the component interconnections) in a higher-level entity-architecture structure. E.g.
--Define components in separate entity-architecture structures in 1 or more VHDL files
-- components.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity c1 is port(...); end c1;
architecture behaviour of c1 is
begin
...
end behaviour;
library ieee; use ieee.std_logic_1164.all;
entity c2 is port(...); end c2;
architecture behaviour of c2 is begin ... end behaviour;
--same for c3
-- define your package.
-- Package all related components here.
-- nosharedsignals.vhdl
library ieee, work;
use ieee.std_logic_1164.all;
use work.components.all;
package noSharedSignals is
component c1 is port(...); end component;
component c2 is port(...); end component;
component c3 is port(...); end component;
function f1(...) return std_logic_vector;
end noSharedSignals;
package body noSharedSignals is
--do not declare shared variables or global signals here if your compiler doesn't support this feature.
-- Define only functions/procedures here
end noSharedSignals;
-- connect components in a different VHDL file. This file can be used by a top-level entity by including it as a component
-- include only components that you want to use from the package. The package should be the full set of components, while this block just connects whatever components that are needed from the package.
--megablock.vhdl
library ieee, work;
use ieee.std_logic_1164.all;
use work.nosharedsignals.all;
entity megablock is port(clk: in std_logic; q: out std_logic); end megablock;
architecture structural of megablock is
component c1 is port(a: in std_logic; b: out std_logic_vector(7 downto 0)); end component;
component c2 is port(c: in std_logic_vector(7 downto 0); d: out std_logic); end component;
signal s:std_logic_vector(7 downto 0);
begin
c1 port map(clk,s);
c2 port map(s,q);
end structural;
--use your megablock in your top-level entity
--system.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity system is port(...); end system;
architecture behaviour of system is
component megablock is port(...); end component;
--declare other components here
begin
--connect your megablock to other blocks in your system, using the same method as in megablock.vhdl
end behaviour;
