GRLIB VHDL IP library available (GPL)

Discussion in 'VHDL' started by Jiri Gaisler, Oct 5, 2004.

  1. Jiri Gaisler

    Jiri Gaisler Guest

    The first beta of the GRLIB VHDL IP library and LEON3 is now available for
    download from:

    http://www.gaisler.com/products/grlib/grlib.html

    Note that this is a first beta release, with some short-comings
    and rough edges. We will improve the documentation and add more
    functionality over then next few weeks.

    To get started, read the GRLIB overview, the GRLIB User's Manual
    and the GRLIB online documentation. GRLIB is a collection of
    parametrizable VHDL IP blocks, which can be put together
    in almost any configuration. While this provides a larger design
    freedom, it also provides many more ways of making mistakes...

    We have added some example designs, including a reference
    design for LEON3 systems. The LEON2 GUI (tkconfig) has been
    ported to the reference design to make configuration easier.
    A short 'Getting started with LEON3' is also provided in
    http://www.gaisler.com/products/grlib/docs/designs/leon3mp/index.html
    The reference design allows SMP systems up to four processors,
    but we have no software for it yet. A port of eCos SMP feature
    is probably the quickest way of getting some SMP functionality.

    Note that you will need new compiler tool-chains for LEON3, the
    old leccs will not work. We have split the new tool-chains in
    two: a pure RTEMS compiler for ERC32/LEON2/LEON3 and a bare-C
    compiler for LEON2 and LEON3. We have also included the source
    code for mkprom and libio (low-level I/O) for LEON3 ..!
    A new GRMON debug tool is also needed, and a linux eval version
    is available. A windows version and some more documentation will
    follow soon. We have a beta LEON3 simulator, and a public eval
    version is not far away.

    In addtion to modelsim and ncsim, the full library (except two verilog
    blocks) can be simulated by the free GNU VHDL (GHDL) compiler.
    Although not as fast as modelsim or ncsim, it is still quite useful.

    For synthesis, scripts for synplify, XST, synopsys DC and cadence RC
    are automatically generated. One issue is however that XST cannot
    be used for synthesis of GRLIB or LEON3 because XST produces incorrect
    netlists. We are working on this issue but it is not easy to find
    workarounds without making the code too ugly.

    Enjoy, Jiri.
     
    Jiri Gaisler, Oct 5, 2004
    #1
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  2. Have you considered creating pages at opencores.org for
    your cores? To me it looks as if opencores.org is the place where
    one can find the most free cores in one place.

    Wishbone-compliant versions would be nice as well, since
    Wishbone seems to be more widespread than Amba among free cores and
    would ease integration.

    Thanks for releasing these great cores under a free license.

    Philipp
     
    Philipp Klaus Krause, Oct 7, 2004
    #2
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  3. Jiri Gaisler

    Jiri Gaisler Guest

    Philipp Klaus Krause <> wrote in message news:<>...
    > Have you considered creating pages at opencores.org for
    > your cores? To me it looks as if opencores.org is the place where
    > one can find the most free cores in one place.


    Opencore uses pre-dominantely verilog, while GRLIB is VHDL. Also, opencores
    have standardized on wishbone, while GRLIB is centered around AMBA bus. No
    much use to put GRLIB on opencores since the GRLIB cores will not fit with
    opencores cores.

    >
    > Wishbone-compliant versions would be nice as well, since
    > Wishbone seems to be more widespread than Amba among free cores and
    > would ease integration.


    Wishbone is not well defined and lacks proper burst transfers. GRLIB is designed
    to be used in commercial designs where AMBA is the standard. We have developed
    a wishbone/AMBA bridge for the opencores ethernet MAC though.

    Regards, Jiri.
     
    Jiri Gaisler, Oct 18, 2004
    #3
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