Hardware implementation of Safer+ algorithm blocks 'e', 'l'

Discussion in 'VHDL' started by Rag, Jan 30, 2006.

  1. Rag

    Rag Guest

    Does any one know how to implement the following expressions in Verilog
    or VHDL..

    These are part of Safer + algorithm implementation.

    That is the implementation of these two expressions

    1. "e" is computation expression is as: y1= 45 exp (x1) in GF(257)

    with exception 45 exp (128) = 0 .

    2. The "l" function is implemented as: y2= log 45 (x2 ) in GF(257)
    with the
    exception log 45 (0) = 128.( Here Log base is 45 ).

    If some one knows how to implemet these expressions please tell me.

    Thanks in advance
     
    Rag, Jan 30, 2006
    #1
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