Having access to a VHDL "signal" using ModelSim

Discussion in 'VHDL' started by =?iso-8859-1?q?Guilherme_Corr=EAa?=, Nov 21, 2006.

  1. Hello,

    I'm just starting to use ModelSim Altera Web Edition and I'm facing
    some problems when I try to access the signals defined in my VHDL code.
    These signal aren't visible in the ModelSim interface after the
    compilation using Quartus II, but I can see the FPGA signals.
    Is there any assertion that I could do to have access to these signals?

    Thanks a lot.
    Guilherme Corrêa.
    =?iso-8859-1?q?Guilherme_Corr=EAa?=, Nov 21, 2006
    #1
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  2. =?iso-8859-1?q?Guilherme_Corr=EAa?=

    KJ Guest

    "Guilherme Corrêa" <> wrote in message
    news:...
    > Hello,
    >
    > I'm just starting to use ModelSim Altera Web Edition and I'm facing
    > some problems when I try to access the signals defined in my VHDL code.
    > These signal aren't visible in the ModelSim interface after the
    > compilation using Quartus II, but I can see the FPGA signals.
    > Is there any assertion that I could do to have access to these signals?
    >
    > Thanks a lot.
    > Guilherme Corrêa.


    Don't use the compilation output file from Quartus for simulation, use your
    input VHDL file.

    KJ
    KJ, Nov 21, 2006
    #2
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  3. Thanks for your answer, KJ.

    Actually, I'm compiling my code with Quartus II because I need the
    information from de FPGA (internal signals, delays, etc.). If I compile
    with Quartus II and simulate with ModelSim, I can obtain these
    information from the FPGA.

    Guilherme Corrêa.


    KJ escreveu:

    > "Guilherme Corrêa" <> wrote in message
    > news:...
    > > Hello,
    > >
    > > I'm just starting to use ModelSim Altera Web Edition and I'm facing
    > > some problems when I try to access the signals defined in my VHDL code.
    > > These signal aren't visible in the ModelSim interface after the
    > > compilation using Quartus II, but I can see the FPGA signals.
    > > Is there any assertion that I could do to have access to these signals?
    > >
    > > Thanks a lot.
    > > Guilherme Corrêa.

    >
    > Don't use the compilation output file from Quartus for simulation, use your
    > input VHDL file.
    >
    > KJ
    =?iso-8859-1?q?Guilherme_Corr=EAa?=, Nov 21, 2006
    #3
  4. =?iso-8859-1?q?Guilherme_Corr=EAa?=

    KJ Guest

    "Guilherme Corrêa" <> wrote in message
    news:...
    > Thanks for your answer, KJ.
    >
    > Actually, I'm compiling my code with Quartus II because I need the
    > information from de FPGA (internal signals, delays, etc.). If I compile
    > with Quartus II and simulate with ModelSim, I can obtain these
    > information from the FPGA.
    >
    > Guilherme Corrêa.


    Then don't expect any of your signal names to show up in the output from
    Quartus. When you run through Quartus (or any other synthesis tool that
    turns VHDL into a bitstream to program the device) it runs through a set of
    operations that optomizes the code that you've written so that it can be
    implemented within the primitives that it has to work with (i.e. look up
    tables and flip flops mostly). One result of that is that basically none of
    your signal names will retain the name that you gave it.

    Some signal names that tend to survive this process are the inputs/outputs
    of the top level of the design and (usually) outputs of flip flops.

    KJ
    KJ, Nov 21, 2006
    #4
  5. Guilherme Corrêa schrieb:


    > I'm just starting to use ModelSim Altera Web Edition and I'm facing
    > some problems when I try to access the signals defined in my VHDL code.
    > These signal aren't visible in the ModelSim interface after the
    > compilation using Quartus II, but ...


    After synthesis a lot of signal names change.

    Often the name of a signal, that is driven by a flipflop is not changed,
    if the signal was not part of a vector. If the signal was part of a
    vector, the signal may be transformed from "my_vector(0)" to
    "my_vector_0" or a similar name.
    Inputs and outputs retain their names.
    If you make the hierarchy flat a signal in a subcomponent may be renamed
    to "subcomponentinstance_mysignal" or similar.

    Have a look into your netlist - let your synthesis tool generate a
    netlist in a format you can read - e.g. VHDL. Search for the desired
    names or parts of the desired name. With some luck you will find them.

    Ralf
    Ralf Hildebrandt, Nov 21, 2006
    #5
  6. Xilinx XST synthesizer has the optiont of keeping the hierarchy when
    going through synthesis... Symplify has somehting like that too. I
    would assume there must be a similar option in Quartus. If you could
    find such an option, you may be able to make sense of the internal
    signals. Keep in mind that the implementation itself will be different
    since you asked the tools not to break the hierarchy of the design...

    On Nov 21, 6:14 am, "KJ" <> wrote:
    > "Guilherme Corrêa" <> wrote in messagenews:...
    >
    > > Thanks for your answer, KJ.

    >
    > > Actually, I'm compiling my code with Quartus II because I need the
    > > information from de FPGA (internal signals, delays, etc.). If I compile
    > > with Quartus II and simulate with ModelSim, I can obtain these
    > > information from the FPGA.

    >
    > > Guilherme Corrêa.Then don't expect any of your signal names to show up in the output from

    > Quartus. When you run through Quartus (or any other synthesis tool that
    > turns VHDL into a bitstream to program the device) it runs through a set of
    > operations that optomizes the code that you've written so that it can be
    > implemented within the primitives that it has to work with (i.e. look up
    > tables and flip flops mostly). One result of that is that basically none of
    > your signal names will retain the name that you gave it.
    >
    > Some signal names that tend to survive this process are the inputs/outputs
    > of the top level of the design and (usually) outputs of flip flops.
    >
    > KJ
    canadianJaouk, Nov 21, 2006
    #6
  7. Guilherme Corrêa wrote:

    > Actually, I'm compiling my code with Quartus II because I need the
    > information from de FPGA (internal signals, delays, etc.)


    Consider using Modelsim to test your code directly
    and Quartus static timing to check timing on
    the routed netlist.

    -- Mike Treseler
    Mike Treseler, Nov 21, 2006
    #7
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