Having access to a VHDL "signal" using ModelSim

Discussion in 'VHDL' started by =?iso-8859-1?q?Guilherme_Corr=EAa?=, Nov 21, 2006.

  1. Hello,

    I'm just starting to use ModelSim Altera Web Edition and I'm facing
    some problems when I try to access the signals defined in my VHDL code.
    These signal aren't visible in the ModelSim interface after the
    compilation using Quartus II, but I can see the FPGA signals.
    Is there any assertion that I could do to have access to these signals?

    Thanks a lot.
    Guilherme CorrĂȘa.
     
    =?iso-8859-1?q?Guilherme_Corr=EAa?=, Nov 21, 2006
    #1
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