Having problems with the following code???

[viv1tyagi]

Hi everyone!!!!!!!!!!
I'm studying vhdl for my college and facing problems running the
following program to implement an UP-DOWN counter. When i compile the
program, no error is shown but when i run it, i receive the
following :-


---------------------------------------------------------------------------------------------------------------------------------------
Error: CSVHE0001: test_updn.vhd: (line 13): Unresolved signal 'u1' has
more than one source
Error: CSVHE0001: test_updn.vhd: (line 13): Unresolved signal 'd1' has
more than one source
Error: CSVHE0001: test_updn.vhd: (line 13): Unresolved signal 'clk1'
has more than one source
Error: CSVHE0001: test_updn.vhd: (line 13): Unresolved signal 'clr1'
has more than one source
Error: CSVHE0001: test_updn.vhd: (line 13): Unresolved signal 'u1' has
more than one source
Error: CSVHE0001: test_updn.vhd: (line 13): Unresolved signal 'd1' has
more than one source
Error: CSVHE0001: test_updn.vhd: (line 13): Unresolved signal 'clk1'
has more than one source
Error: CSVHE0001: test_updn.vhd: (line 13): Unresolved signal 'clr1'
has more than one source
Error: CSVHE0001: test_updn.vhd: (line 13): Unresolved signal 'u1' has
more than one source
Error: CSVHE0001: test_updn.vhd: (line 13): Unresolved signal 'd1' has
more than one source
Error: CSVHE0001: test_updn.vhd: (line 13): Unresolved signal 'clk1'
has more than one source
Terminating run because of too many errors!
Error: Failed to connect to simulator 'vhdle'!!
-------------------------------------------------------------------------------------------------

I'm new to this language and hence can't figure out what's the
problem.
So please help.
Here are the 4 files:
1.) UPDN.vhd
2.) UPDN_TFF.vhd
3.) UPDN_COMP.vhd
4.)TEST_UPDN.vhd


--------------------------------------------------------------------------------
--UPDN.vhd

library IEEE;
use ieee.std_logic_1164.all;

entity updn is
port(up,down,clock,clear : in bit;
outp : out bit_vector(3 downto 0));
end entity;

architecture arch_updn of updn is
component tff is
port ( in1,in2,clk,reset : in bit;
q : out bit);
end component;

component comp1 is
port(ups,dns,ops : in bit;
upside,downside : out bit);
end component;

signal Q,U,D : bit_vector(3 downto 0) ;
begin
tff0 : tff port map (up,down,clock,clear,Q(0));
comp10 : comp1 port map (up,down,Q(0),U(0),D(0));

tff1 : tff port map (U(0),D(0),clock,clear,Q(1));
comp11 : comp1 port map (Q(0),(not Q(0)),Q(1),U(1),D(1));

tff2 : tff port map (U(1),D(1),clock,clear,Q(2));
comp12 : comp1 port map (Q(1),(not Q(1)),Q(2),U(2),D(2));

tff3 : tff port map (U(2),D(2),clock,clear,Q(3));
comp13 : comp1 port map (Q(2),(not Q(2)),Q(3),U(3),D(3));

outp <= Q;
end arch_updn;
-----------------------------------------------------------------------------------

-----------------------------------------------------------------------------------
--UPDN_TFF.vhd
entity tff is
port ( in1,in2,clk,reset : in bit;
q : out bit);
end entity;


architecture tff_arch of tff is
begin
process (clk,reset)
variable temp : bit;
begin
if (reset = '1') then
temp :='0';
elsif (clk'event and clk='1' and in1='0' and in2='0') then
temp := temp;
elsif (clk'event and clk='1' and (in1='1' or in2='1')) then
temp := not temp;
end if;
q <=temp;
end process;
end tff_arch;

-----------------------------------------------------------------------------------

---------------------------------------------------------------------------------------
--UPDN_COMP.vhd
library IEEE;
use ieee.std_logic_1164.all;

entity comp1 is
port(ups,dns,ops : in bit;
upside,downside : out bit);
end entity;

architecture arch_comp1 of comp1 is
begin
--tff <= ups or dns;
upside <= ups and ops;
downside <= dns and (not ops);
end arch_comp1;

-------------------------------------------------------------------------

------------------------------------------------------------------------
--TEST_UPDN.vhd
library IEEE;
use ieee.std_logic_1164.all;

entity test_updn is
end entity;

architecture arch_test_updn of updn is
component updn is
port(up,down,clock,clear : in bit;
outp : out bit_vector(3 downto 0));
end component;

signal u1,d1,clk1,clr1 : bit;
signal OUTPUT : bit_vector(3 downto 0);

begin
inst : updn port map (u1,d1,clk1,clr1,OUTPUT);
process
begin
u1 <= '1';
d1 <= '0';
wait for 40 ns;

u1 <= '0';
d1 <= '1';
wait for 30 ns;
end process;

process
begin
clk1 <= '0';
clr1 <= '0';
wait for 10 ns;

clk1 <= '1';
clr1 <= '0';
wait for 10 ns;
end process;

end arch_test_updn;

 

[Mike Treseler]

I'm studying vhdl for my college and facing problems running the
following program to implement an UP-DOWN counter. When i compile the
program, no error is shown but when i run it, i receive the
following :-

http://www.google.com/search?q=vhdl+up+down+counter+example+numeric_std

 

[sandeep]

http://www.google.com/search?q=vhdl+up+down+counter+example+numeric_std

First you should decide whether you want to use type BIT or type
STD_LOGIC and then accordingly include library and package.

 

[Peter]

Please HELP!!!!!!!!!!!!!!!!!!

You dont utilize the power of VHDL by describing low level elements
and putting them together in a structure. If you want an up-down
counter then just write the code for what you want a let synthesis
figure out how to put the flip-flops together. Use the standard
template for synchronous processes mentioned many times in this group
and preferably types from the ieee.numeric_std library.

/Peter

 

[viv1tyagi]

I ma asking all of you what's wrong with my code and not how i should
be doing it. So if any one of you can tell me what's wrong with it
and HOW SHOULD I CORRECT IT without using STD_LOGIC or behavioral
modeling or any other thing like that, PLEASE HELP.

 

[Mike Treseler]

I ma asking all of you what's wrong with my code and not how i should
be doing it. So if any one of you can tell me what's wrong with it
and HOW SHOULD I CORRECT IT without using STD_LOGIC or behavioral
modeling or any other thing like that, PLEASE HELP.

There is almost nothing right about your code.
The quickest solution is to start over after
looking at a few working examples and trying
them with your tools.

To debug code, I use simulation and an rtl viewer.
The newsgroup can only handle simple specific questions.

-- Mike Treseler

 

[KJ]

 I ma asking all of you what's wrong with my code and not how i should
be doing it. So if  any one of you can tell me what's wrong with it
and HOW SHOULD I CORRECT IT without using STD_LOGIC or behavioral
modeling or any other thing like that, PLEASE HELP.

One of the three is obvious:
1. Whatever software you're using that is misleading you into
believing "When i compile the program, no error is shown" is
useless...get rid of it if possible.
2. The code you posted is not the code you're trying to run.
3. You completely missed the error messages.

When running your posted code through Modelsim I get the following
compile errors:

** Error: C:\Sim\Ocr2k_Sim\HDL\Ocr2K_Fpga\Ocr2K_Fpga.vhd(680): Actual
(prefix expression) for formal "dns" is not a globally static
expression.
** Error: C:\Sim\Ocr2k_Sim\HDL\Ocr2K_Fpga\Ocr2K_Fpga.vhd(684): Actual
(prefix expression) for formal "dns" is not a globally static
expression.
** Error: C:\Sim\Ocr2k_Sim\HDL\Ocr2K_Fpga\Ocr2K_Fpga.vhd(688): Actual
(prefix expression) for formal "dns" is not a globally static
expression.
** Error: C:\Sim\Ocr2k_Sim\HDL\Ocr2K_Fpga\Ocr2K_Fpga.vhd(692): VHDL
Compiler exiting

Where the offending lines are shown below.
Line 680: comp11 : comp1 port map (Q(0),(not Q(0)),Q(1),U(1),D(1));
Line 684: comp12 : comp1 port map (Q(1),(not Q(1)),Q(2),U(2),D(2));
Line 688: comp13 : comp1 port map (Q(2),(not Q(2)),Q(3),U(3),D(3));

The error messages are correct and not terribly hard to understand
(i.e. component output signals need to be simply that...simple
signals).

Presumably when you fix those three errors others will pop up. Keep
iterating until you really get no errors during a compile.

Kevin Jennings

 

[sandeep]

One of the three is obvious:
1. Whatever software you're using that is misleading you into
believing "When i compile the program, no error is shown" is
useless...get rid of it if possible.
2. The code you posted is not the code you're trying to run.
3. You completely missed the error messages.

When running your posted code through Modelsim I get the following
compile errors:

** Error: C:\Sim\Ocr2k_Sim\HDL\Ocr2K_Fpga\Ocr2K_Fpga.vhd(680): Actual
(prefix expression) for formal "dns" is not a globally static
expression.
** Error: C:\Sim\Ocr2k_Sim\HDL\Ocr2K_Fpga\Ocr2K_Fpga.vhd(684): Actual
(prefix expression) for formal "dns" is not a globally static
expression.
** Error: C:\Sim\Ocr2k_Sim\HDL\Ocr2K_Fpga\Ocr2K_Fpga.vhd(688): Actual
(prefix expression) for formal "dns" is not a globally static
expression.
** Error: C:\Sim\Ocr2k_Sim\HDL\Ocr2K_Fpga\Ocr2K_Fpga.vhd(692): VHDL
Compiler exiting

Where the offending lines are shown below.
Line 680: comp11 : comp1 port map (Q(0),(not Q(0)),Q(1),U(1),D(1));
Line 684: comp12 : comp1 port map (Q(1),(not Q(1)),Q(2),U(2),D(2));
Line 688: comp13 : comp1 port map (Q(2),(not Q(2)),Q(3),U(3),D(3));

The error messages are correct and not terribly hard to understand
(i.e. component output signals need to be simply that...simple
signals).

Presumably when you fix those three errors others will pop up.  Keep
iterating until you really get no errors during a compile.

Kevin Jennings

There are two problem with your code. First is pointed by KJ and
second is
typo in following line
architecture arch_test_updn of updn is
of file TEST_UPDN.vhd .

In the beginning it is always difficult to understand the error
message since book
doesnot talk about all these. You need to have patience and carefully
go through the log file
to understand the error.