'HDL-27 Constant value required' when using signal as index

Discussion in 'VHDL' started by woutput, Nov 27, 2008.

  1. woutput

    woutput

    Joined:
    Nov 27, 2008
    Messages:
    2
    I hope you can help me on this problem, I've been working on it for some days now.

    When I simulate the following VHDL code, I receive no errors and the results are good.
    Part of my code:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;--to use to_integer()
    ...
    generic
    (
    AXI_ADDR_DATA_BITS : integer := 32;
    VPAGE_BITS : integer := 12;
    VPAGE_SETTING_BITS : integer := 3;
    VPAGE_SETTING_OFFSET : integer := 10
    )
    port
    (
    PAGE_SIZE_SETTING : in std_logic_vector(VPAGE_SETTING_BITS - 1 downto 0);
    VIR_ADDRESS_PAGE : out std_logic_vector(VPAGE_BITS - 1 downto 0);
    VIR_ARAW_ADDR : in std_logic_vector(AXI_ADDR_DATA_BITS - 1 downto 0);
    )
    ...
    VIR_ADDRESS_PAGE <=
    VIR_ARAW_ADDR
    (
    VPAGE_BITS
    +
    to_integer
    (
    unsigned
    (
    PAGE_SIZE_SETTING
    )
    )
    +
    VPAGE_SETTING_OFFSET
    -
    1
    downto
    to_integer
    (
    unsigned
    (
    PAGE_SIZE_SETTING
    )
    )
    +
    VPAGE_SETTING_OFFSET
    );

    But when I synthesise it, I get the following error: HDL-27 Constant value required
    When I look up the error description (2nd hit: google for "constant value required" vhdl), it is not clear to me why this is not possible. I could image a combinatorial circuit (with a lot of multiplexers) which could solve this problem.
    When I replace "to_integer(unsigned(PAGE_SIZE_SETTING))" with "3" it synthesises too. Like this:

    VIR_ADDRESS_PAGE <=
    VIR_ARAW_ADDR
    (
    VPAGE_BITS
    +
    3
    +
    VPAGE_SETTING_OFFSET
    -
    1
    downto
    3
    +
    VPAGE_SETTING_OFFSET
    );

    To solve this problem, I tried the following code:

    FIX : for I in (to_integer(unsigned(PAGE_SIZE_SETTING)) + VPAGE_SETTING_OFFSET) to (VPAGE_BITS + to_integer(unsigned(PAGE_SIZE_SETTING)) + VPAGE_SETTING_OFFSET - 1) loop
    VIR_ADDRESS_PAGE(I - (to_integer(unsigned(PAGE_SIZE_SETTING)) + VPAGE_SETTING_OFFSET)) <= VIR_ARAW_ADDR(I);
    end loop FIX;

    but I get the same error again. When applying the replace, it "works" again. Like this:

    FIX : for I in (3 + VPAGE_SETTING_OFFSET) to (VPAGE_BITS + 3 + VPAGE_SETTING_OFFSET - 1) loop
    VIR_ADDRESS_PAGE(I - (3 + VPAGE_SETTING_OFFSET)) <= VIR_ARAW_ADDR(I);
    end loop FIX;

    Can you give me a hint to solve my problem please?
    I guess that my problem is "just" indexing a std_logic_vector with a signal as index.

    Thank you in advance,
    Wouter

    Simulation: ModelSim SE 6.3a
    Synthesis: Synopsys Design Analyzer
     
    woutput, Nov 27, 2008
    #1
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  2. woutput

    woutput

    Joined:
    Nov 27, 2008
    Messages:
    2
    I solved the problem with help from someone else:

    Now I have

    VIR_ADDRESS_PAGE <= (others => '0');
    FILL_VIR_ADDRESS_PAGE : for I in (0 + VPAGE_SETTING_OFFSET) to (VPAGE_BITS + (2**VPAGE_SETTING_BITS - 1) + VPAGE_SETTING_OFFSET - 1) loop
    if ((I > (to_integer(unsigned(PAGE_SIZE_SETTING)) + VPAGE_SETTING_OFFSET)) and (I < (VPAGE_BITS + to_integer(unsigned(PAGE_SIZE_SETTING)) + VPAGE_SETTING_OFFSET - 1))) then
    VIR_ADDRESS_PAGE(I - (to_integer(unsigned(PAGE_SIZE_SETTING)) + VPAGE_SETTING_OFFSET)) <= VIR_ARAW_ADDR(I);
    end if;
    end loop FILL_VIR_ADDRESS_PAGE;
     
    woutput, Dec 3, 2008
    #2
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