HDL Hierarchy Manager 1.2.1 Announcement

Discussion in 'VHDL' started by Alan, Oct 2, 2003.

  1. Alan

    Alan Guest

    Prime Technology announced today the release of HDL Hierarchy Manager
    version 1.2.1 (HHM). HHM is a quick and easy to use tool for browsing
    Verilog and VHDL source code, project/library management, design
    hierarchy and structural code generation.

    HHM allows you to automatically generate structural HDL code for
    sub-blocks as well as your chip's top-level in seconds. It can quickly
    import existing design and automatically display its hierarchy in a
    tree structure. The source code can then be easily navigated and
    detailed structural information can be displayed in a series of
    tables. The interconnect for an existing hierarchy level can be
    modified in the tables and the HDL source code can be regenerated.

    A new hierarchy level can be created by selecting components from
    imported libraries which can then be automatically connected. The new
    structure can be generated in either Verilog or VHDL, imported and the
    project hierarchy automatically updated.

    You can get more information using these links:
    - Screen shots - www.prime-tec.com/hhm/screenshots.htm
    - Overview - www.prime-tec.com/hhm/overview.htm
    - Features - www.prime-tec.com/hhm/features.htm
    - Download - www.prime-tec.com/hhm/download.htm


    HHM takes care of the tedious aspects of ASIC and FPGA design, leaving
    you free to create.
     
    Alan, Oct 2, 2003
    #1
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