HDLScore Code coverage FSM extraction

Discussion in 'VHDL' started by Tony Smith, Apr 28, 2004.

  1. Tony Smith

    Tony Smith Guest

    Hi,

    I am mucking about with the HDLScore code coverage tool (through
    Cadence).
    I am attempting FSM extraction but am having problems with the 'conv'
    functions in the RTL.
    I set_fsm_attribute correctly, then extract_fsm successfully.
    However, my scripts fail due to 'conv_integer' and
    'conv_std_logic_vector' in the RTL.

    has anyone had this problem? or any ideas to solve it?

    Thanks in advance,
    Tony
     
    Tony Smith, Apr 28, 2004
    #1
    1. Advertisements

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Abs
    Replies:
    6
    Views:
    2,095
  2. milesd
    Replies:
    4
    Views:
    1,874
    Dale King
    Aug 29, 2003
  3. bill turner
    Replies:
    2
    Views:
    1,366
    bill turner
    Jul 19, 2005
  4. Raj
    Replies:
    4
    Views:
    8,493
    asicvlsi
    Feb 21, 2008
  5. hari_krishna

    FSM State transition coverage

    hari_krishna, Aug 22, 2006, in forum: VHDL
    Replies:
    0
    Views:
    1,097
    hari_krishna
    Aug 22, 2006
  6. Ben Finney
    Replies:
    7
    Views:
    789
    Ned Batchelder
    Oct 30, 2007
  7. Replies:
    0
    Views:
    592
  8. Hussein B

    Code coverage to Python code

    Hussein B, Jan 4, 2009, in forum: Python
    Replies:
    6
    Views:
    597
    Kay Schluehr
    Jan 5, 2009
Loading...