help about conversion!

Discussion in 'VHDL' started by loris, Jul 18, 2008.

  1. loris

    loris

    Joined:
    Jul 18, 2008
    Messages:
    3
    Hi all,
    I am new to VHDL.
    My problem is this:

    I have defined in a package the type data_out,as following:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    constant width : INTEGER := 4;
    type data_out is array(0 to width-1) of std_logic;

    Then I have as output:
    data : out data_out;

    and also a signal (maned sig) as std_logic_vector(0 to width-1).
    So, when I calculate the expression of sig and finally I want to assign it to data (of type data_out) , I have an error message that says:<<Type of data is incompatible with type of sig>>.
    But, an array of standar_logic, is not equal to a standard_logic_vector?
    How can I resolve the problem?
    Please, help me :-(

    tnx to all
     
    loris, Jul 18, 2008
    #1
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  2. loris

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Well - a quick answer or two:

    1) The definition array not compatible with vector
    2) you could consider using the "subtype" definition in order to make your own vector type.
    3) you could make a procedure or function which could convert from the vector type to your array type.

    Your welcome
    Jeppe

    If Im in the mode and have time will I try it later. :)
     
    jeppe, Jul 18, 2008
    #2
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