Help!!!! Async internal signal generation

Discussion in 'VHDL' started by sonny, Oct 26, 2007.

  1. sonny

    sonny Guest

    Hi

    i am just a newbie and need some help...... i need to generate reset
    signal using many internal signals... in simulations, it works fine,
    but not sure how it synthesizes the process down below.... i know this
    code is not really nice, but have no clue how to make it better....
    plz help me out with this.... any help would be very helpful.... thx
    in advance.

    sonny


    p_rst : process(dly_ctrl_a_i, dly_rst_i, int_flg_s, over_flow_s,
    ctlr_rst_s, mix_subphase, capt_en_mix_s)
    begin
    if ctlr_rst_s = '1' or capt_en_mix_s = '1' or mix_subphase
    = '1' then
    if dly_ctrl_a_i = '1' then
    rst_s <= '1';
    end if;
    if rising_edge(over_flow_s) then
    rst_s <= '0';
    elsif falling_edge(int_flg_s) then
    rst_s <= '0';
    elsif falling_edge (dly_rst_i) then
    rst_s <= '0';
    end if;
    else
    rst_s <= '0';
    end if;
    end process;
    sonny, Oct 26, 2007
    #1
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  2. sonny schrieb:


    > p_rst : process(dly_ctrl_a_i, dly_rst_i, int_flg_s, over_flow_s,
    > ctlr_rst_s, mix_subphase, capt_en_mix_s)
    > begin
    > if ctlr_rst_s = '1' or capt_en_mix_s = '1' or mix_subphase
    > = '1' then
    > if dly_ctrl_a_i = '1' then
    > rst_s <= '1';
    > end if;
    > if rising_edge(over_flow_s) then
    > rst_s <= '0';
    > elsif falling_edge(int_flg_s) then
    > rst_s <= '0';
    > elsif falling_edge (dly_rst_i) then
    > rst_s <= '0';
    > end if;
    > else
    > rst_s <= '0';
    > end if;
    > end process;


    Don't use rising_edge / falling_edge nested in if clauses.
    Don't use twice rising_endge / falling_edge.


    Stick to the synchronous process template:

    process(async_reset,clk)
    begin
    if (async_reset='0') then
    -- do some asynchronous reset
    elsif rising_edge(clk) then
    -- do some synchronous stuff
    end if;
    end process;


    Ask yourself: Do you really need both the falling_edge of int_flg_s and
    the falling_edge of dly_rst_i? Is it possible to just use the level of
    one of these signals? What about sampling these signals with a (fast) clock?


    Remember, that rst_s needs a reset itself!


    Ralf
    Ralf Hildebrandt, Oct 26, 2007
    #2
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