help conversion code

[srinukasam]

hi
i need a code for converting std_logic_vector to array of diiferent
width.

i wrote code, but its not working at the simulation time..its giving error
that INDEX 27 IS OUTOF RANGE FOR 23 DOWNTO 0:

MY CODE

ENTITY mux_gene IS

generic ( size :integer :=16; --input signal width
ictrl_width :integer :=4; -- individual control signal
width
tctrl_width : integer :=24; -- total control signal
width--mem out
no_out,no_ctrl :integer :=6); -- no of output
signals(r),no.of control signals (V)

port(clk : in std_logic;
input : in std_logic_vector( size-1 downto 0);
ctrl : in std_logic_vector( tctrl_width-1 downto 0);
mux_out : out std_logic_vector(no_out-1 downto 0);
--z : OUT out_gen);
reset : in std_logic);

END ENTITY mux_gene;
--
ARCHITECTURE mux_gene_beh OF mux_gene IS

signal ctrl_arr : ctrl_gen( 0 to no_ctrl-1);
signal z : out_gen;

BEGIN


sortrocess(ctrl)

variable first:integer:=0;
variable second:integer:=0;
variable temp :std_logic_vector(ictrl_width-1 downto 0);
begin
assign:for i in 0 to no_ctrl-1 loop
if i=0 then
ctrl_arr(i) <=ctrl(ictrl_width-1 downto 0);
else
first:=first+ictrl_width;
second:=first+(ictrl_width-1);
temp:= ctrl(second downto first);
ctrl_arr(i) <= temp;
end if;
end loop assign;
wait;
end process sort;

pls help me by sending new code or by sending error in my code.
thank you
bye