Help creating SDRAM circuit

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Dec 10, 2013
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English to use my might very funny. Because I am not good at English.

I have been using de2-115.
I would like to create a SDRAM circuit to verify that the data is written to the SDRAM, data is read from the SDRAM.
But since I do not understand about the SDRAM circuit , it is difficult .

Could you tell me the code and its operation to me someone ?

By the way , the code shown below is a SRAM circuit that created me.
I would like to create SDRAM something similar to this circuit .


library ieee;
use ieee.std_logic_1164.all;

entity top_level_entity is
port (
 SW: in std_logic_vector (17 downto 0);
 LEDR: out std_logic_vector (17 downto 0);

 SRAM_ADDR: out std_logic_vector (19 downto 0);
 SRAM_DQ: inout std_logic_vector (15 downto 0);
 SRAM_CE_N: out std_logic;
 SRAM_OE_N: out std_logic;
 SRAM_WE_N: out std_logic;
 SRAM_UB_N: out std_logic;
 SRAM_LB_N: out std_logic
) ;
end top_level_entity;


architecture inside_top_level_entity of top_level_entity is

 signal address: std_logic_vector (1 downto 0);
 signal data: std_logic_vector (14 downto 0);
 signal output: std_logic_vector (14 downto 0);
 signal we: std_logic;

begin

 SRAM_WE_N <= not SW (15);

 SRAM_CE_N <= '0 ';
 SRAM_OE_N <= '0 ';
 SRAM_UB_N <= '0 '; 
 SRAM_LB_N <= '0 ';

 address <= SW (17 downto 16);
 SRAM_ADDR (19 downto 2) <= (others => '0 ');
 SRAM_ADDR (1 downto 0) <= address;

 data <= SW (14 downto 0) when SW (15) = '1 'else (others =>' Z ');
 SRAM_DQ (15) <= '0 ';
 SRAM_DQ (14 downto 0) <= data;

 output <= SRAM_DQ (14 downto 0);
 LEDR (14 downto 0) <= output;

end inside_top_level_entity;




help, help, sir, for the love of Heaven.
 
Last edited:

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