Help: Design Compiler does not instantiate Asic's Library's FullAdder

[Nikolaos Kefalas]

I am using Design Compiler, with tsmc 0.13 Asic library.
The tsmc library provides full adder cell but Design Compiler is not
using it.
I instantiated a full adder using the component instantiation as
descripted in Designware User Guide.

library IEEE, GTECH;
use IEEE.std_logic_1164.all;
use GTECH.GTECH_components.all;
entity GT_add_abc_inst is
port(in1, in2, cin : in std_logic;
sum, cout : out std_logic);
end GT_add_abc_inst;
architecture sim of GT_add_abc_inst is
begin
U1 : GTECH_ADD_ABC
port map(A => in1, B => in2,
C => cin,
S => sum, COUT => cout);
end sim;

Design Compiler compiled this full adder with primitive cells.
How i can instruct DC to use the full adder cell from the Asic Library ?
It is possible to instantiate direct from VHDL the full adder from the
Asic Library ?

many thanks
nkef

 

[Ralf Hildebrandt]

I am using Design Compiler, with tsmc 0.13 Asic library.
The tsmc library provides full adder cell but Design Compiler is not
using it.

I have monitored this behavior for several versions of Synopsys Design
Analyzer, too. My conclusion was: The fulladder cell in the library is
just too big or too slow.
If you want to verify this - have a look into the VITAL descriptions of
the fulladder and the other primitive cells. You will find the delays there.

You should not instantiate a generic fulladder, because then you have to
provide also this generic library. Just use the addition operator "+".
Synthesis tools handle this very well and you get readable code.

Ralf

 

[mk]

I am using Design Compiler, with tsmc 0.13 Asic library.
The tsmc library provides full adder cell but Design Compiler is not
using it. ....
How i can instruct DC to use the full adder cell from the Asic Library ?
It is possible to instantiate direct from VHDL the full adder from the
Asic Library ?

There maybe several reasons why DC is not using the full adder in the
library. As the op says, it might be too slow or big, or you may not
be constraining your design for it to infer it, it maybe set to
dont_utilize in the library (do a report_library and see if it has
been marked as dont_utilize). You can certainly instantiate it in your
rtl but then the rtl description would be dependent on that library
and you may have the benefit of using a slower/bigger design. Just use
'+' in your design and constrain it properly. DC will generate the
best design; almost always anyway.