Help:efficient FSM coding

Discussion in 'VHDL' started by msd, Feb 22, 2005.

  1. msd

    msd Guest

    Hi everybody.
    I´d like to write an efficient fsm controller to control a AX88796
    ethernet mac/phy from a Xilinx FPGA. The interface of the mac/phy is
    similar to a SRAM. The problem is that I have no idea, how I should
    make the code indipendent from the clock frequency, to respect all
    setup and hold constraints. How do I control that the state of the fsm
    changes only after a paramatrized number of clock cycles, without
    inferring counters and comparators (which wouldn't achieve a ~70MHz
    performance)?

    Best Regards
    Marco
    msd, Feb 22, 2005
    #1
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  2. msd wrote:

    > The problem is that I have no idea, how I should
    > make the code indipendent from the clock frequency, to respect all
    > setup and hold constraints.


    Consider a synchronous design using the same clock as the mac/phy.

    > How do I control that the state of the fsm
    > changes only after a paramatrized number of clock cycles, without
    > inferring counters and comparators


    Those will be inferred, but it is not a problem.

    (which wouldn't achieve a ~70MHz performance)?

    70Mhz should be easy to achieve.


    -- Mike Treseler
    Mike Treseler, Feb 22, 2005
    #2
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