HELP: High fanout load on Gated clock output

Discussion in 'VHDL' started by whizkid, Nov 12, 2004.

  1. whizkid

    whizkid Guest

    Hi Friends,
    I am doing a module design in which I wanted to implement
    module/block level clock gating.
    If there is an enable I want the clock to reach DFFs otherwise not. I
    have been coding the RTL like

    always@(posedge CLK or negedge RST) begin
    if(!RST) begin
    MUX_IN_COUNTER <= 5'b00000;
    end
    else if(ENB) begin
    MUX_IN_COUNTER<= n_MUX_IN_COUNTER;
    end
    end

    All the registers are gated with ENB pin. and I am using DC & power
    compiler to synthesis this RTL .
    Power compiler infers a Integrated clock gate cell , as I have
    specified using the set_clock_gating_style command.
    Power compiler infers one clock gate cell for each verilog sub_module
    (though all the flops are gated by same enable).The problem is there
    are around 6000 flops in my design. and some modules contain upto 800
    flops. Due to fanout load on these highly loaded ICGs(Integrated clock
    gate cells) the gated clock output is getting delayed to upto 30-35%.
    Due to this I am getting lot of violations in netlist simulations
    though Design compiler says My timing is easily Met..

    Can anyone please suggest a solution ??

    One solution I am thinking about is to force DC to take more clock
    gate cells(say one CG cell for 40 flops) instead of one to load 800
    flops. but i dont know how to do it.. does anyone know it ??


    thanks
    Whizkid
     
    whizkid, Nov 12, 2004
    #1
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  2. whizkid

    mk Guest

    On 11 Nov 2004 21:10:02 -0800, (whizkid) wrote:

    >Hi Friends,
    > I am doing a module design in which I wanted to implement
    >module/block level clock gating.
    > If there is an enable I want the clock to reach DFFs otherwise not. I
    >have been coding the RTL like
    >
    > always@(posedge CLK or negedge RST) begin
    > if(!RST) begin
    > MUX_IN_COUNTER <= 5'b00000;
    > end
    > else if(ENB) begin
    > MUX_IN_COUNTER<= n_MUX_IN_COUNTER;
    > end
    > end
    >
    >All the registers are gated with ENB pin. and I am using DC & power
    >compiler to synthesis this RTL .
    >Power compiler infers a Integrated clock gate cell , as I have
    >specified using the set_clock_gating_style command.
    >Power compiler infers one clock gate cell for each verilog sub_module
    >(though all the flops are gated by same enable).The problem is there
    >are around 6000 flops in my design. and some modules contain upto 800
    >flops. Due to fanout load on these highly loaded ICGs(Integrated clock
    >gate cells) the gated clock output is getting delayed to upto 30-35%.
    >Due to this I am getting lot of violations in netlist simulations
    >though Design compiler says My timing is easily Met..
    >
    >Can anyone please suggest a solution ??
    >
    >One solution I am thinking about is to force DC to take more clock
    >gate cells(say one CG cell for 40 flops) instead of one to load 800
    >flops. but i dont know how to do it.. does anyone know it ??


    You need to stop DC buffering the clock nets and run clock tree
    synthesis after logic synthesis and power compiler. DC is not the
    right tool for clock tree management.
     
    mk, Nov 12, 2004
    #2
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  3. whizkid

    whizkid Guest

    mk<> wrote in message

    > You need to stop DC buffering the clock nets and run clock tree
    > synthesis after logic synthesis and power compiler. DC is not the
    > right tool for clock tree management.


    Hi,
    Thanks for the reply. But I think DC is not buffering the Clock tree.
    I use
    constraint "set_dont_touch_network CLK" in my design. Is this what you
    are reffering to ???

    thanks
    Whizkid
     
    whizkid, Nov 13, 2004
    #3
  4. whizkid

    Mark Guest

    Have you run the command :

    set_clock_gating_style

    if not, do a "man set_clock_gating_style" within dc and in particular
    look at the max_fanout switch.

    an example clock gating setup would be would be:

    set power_preserve_rtl)hier_names true
    set hdlin_no_group_register true

    set_clock_gating_style -sequential_cell latch -minimum_bitwidth 4
    -positive_edge_logic {integrated} -max_fanout 64 -control_point none

    (whizkid) wrote in message news:<>...
    > Hi Friends,
    > I am doing a module design in which I wanted to implement
    > module/block level clock gating.
    > If there is an enable I want the clock to reach DFFs otherwise not. I
    > have been coding the RTL like
    >
    > always@(posedge CLK or negedge RST) begin
    > if(!RST) begin
    > MUX_IN_COUNTER <= 5'b00000;
    > end
    > else if(ENB) begin
    > MUX_IN_COUNTER<= n_MUX_IN_COUNTER;
    > end
    > end
    >
    > All the registers are gated with ENB pin. and I am using DC & power
    > compiler to synthesis this RTL .
    > Power compiler infers a Integrated clock gate cell , as I have
    > specified using the set_clock_gating_style command.
    > Power compiler infers one clock gate cell for each verilog sub_module
    > (though all the flops are gated by same enable).The problem is there
    > are around 6000 flops in my design. and some modules contain upto 800
    > flops. Due to fanout load on these highly loaded ICGs(Integrated clock
    > gate cells) the gated clock output is getting delayed to upto 30-35%.
    > Due to this I am getting lot of violations in netlist simulations
    > though Design compiler says My timing is easily Met..
    >
    > Can anyone please suggest a solution ??
    >
    > One solution I am thinking about is to force DC to take more clock
    > gate cells(say one CG cell for 40 flops) instead of one to load 800
    > flops. but i dont know how to do it.. does anyone know it ??
    >
    >
    > thanks
    > Whizkid
     
    Mark, Nov 15, 2004
    #4
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