HELP. How to generate a single delayed pulse strobe in VHDL

Discussion in 'VHDL' started by LRCR, Jul 28, 2006.

  1. LRCR

    LRCR Guest

    This may seem an elementary VHDL question to all of you, but I am an
    analog designer that is learning how to use VHDL in some of my
    projects. Can anyone show me how to write a simple VHDL code that
    generates a single delayed pulse strobe anytime its triggered by a
    single pulse input signal. I have a 1 MHz source connected to my
    Altera FPGA that can be used in this application. Any Help is
    appreciated. Thanks in advance.
     
    LRCR, Jul 28, 2006
    #1
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  2. Re: HELP. How to generate a single delayed pulse strobe in VHDL

    Hi,

    LRCR schrieb:
    > This may seem an elementary VHDL question to all of you, but I am an
    > analog designer that is learning how to use VHDL in some of my
    > projects. Can anyone show me how to write a simple VHDL code that
    > generates a single delayed pulse strobe anytime its triggered by a
    > single pulse input signal. I have a 1 MHz source connected to my
    > Altera FPGA that can be used in this application. Any Help is
    > appreciated. Thanks in advance.


    There are several ways. The best would be a pipelined delay by several
    clocks.

    signal my_sr : std_ulogic_vector(PIPELINE-1 downto 0)
    process(clk)
    my_sr <= my_sr(PIPELINE-2 downto 0) & sig_to_be_delayed;
    end process;
    delayed_sig<= my_sr(PIPELINE-1);


    Another solution is a delay with NOT-gates (or any other gates). This
    requires more effort in synthesis to avoid that your synthesis tool
    removes the delay and you should be aware of variance of delays over
    temperature, voltage and wafer lot.

    bye Thomas
     
    Thomas Stanka, Jul 28, 2006
    #2
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  3. LRCR

    Frank Buss Guest

    Re: HELP. How to generate a single delayed pulse strobe in VHDL

    Thomas Stanka wrote:

    > signal my_sr : std_ulogic_vector(PIPELINE-1 downto 0)
    > process(clk)
    > my_sr <= my_sr(PIPELINE-2 downto 0) & sig_to_be_delayed;
    > end process;
    > delayed_sig<= my_sr(PIPELINE-1);


    With "process(clk)" you specify the sensitivity list, only, so it might run
    in a simulator, but not when synthesized, because the shift runs unclocked
    with maximum speed, which depends on the part, temperature etc.

    I've designed it as a reusable entity:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity shifter is
    generic(pipeline_length: integer);
    port(
    clock: in std_logic;
    data_in: in std_logic;
    data_out: out std_logic);
    end entity shifter;

    architecture rtl of shifter is
    signal shift_register: unsigned(pipeline_length downto 0);

    begin
    shift: process(clock)
    begin
    if clock'event and clock = '1' then
    shift_register <= shift_register sll 1;
    shift_register(0) <= data_in;
    end if;
    end process;

    data_out <= shift_register(shift_register'left);
    end architecture rtl;


    For testing on my Spartan 3E kit, I've used it like this:


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity test is
    port(
    clk_50mhz: in std_logic;
    btn_south: in std_logic;
    led: out unsigned(7 downto 0));
    end entity test;

    architecture rtl of test is
    constant system_speed: natural := 50e6;

    signal clock_10hz: std_logic;
    signal shift_register: unsigned(10 downto 0) := (others => '0');

    begin
    clock_10hz_generator: entity clock_generator
    generic map(clock_in_speed => system_speed, clock_out_speed => 10)
    port map(
    clock_in => clk_50mhz,
    clock_out => clock_10hz);

    shifter_10_bits: entity shifter
    generic map(pipeline_length => 10)
    port map(
    clock => clock_10hz,
    data_in => btn_south,
    data_out => led(0));

    led(1) <= btn_south;
    led(2) <= clock_10hz;
    led(7 downto 3) <= (others => '0');

    end architecture rtl;



    With this general usable clock divider:



    entity clock_generator is
    generic(clock_in_speed, clock_out_speed: integer);
    port(
    clock_in: in std_logic;
    clock_out: out std_logic);
    end entity clock_generator;

    architecture rtl of clock_generator is

    function num_bits(n: natural) return natural is
    begin
    if n > 0 then
    return 1 + num_bits(n / 2);
    else
    return 1;
    end if;
    end num_bits;

    constant max_counter: natural := clock_in_speed / clock_out_speed / 2;
    constant counter_bits: natural := num_bits(max_counter);

    signal counter: unsigned(counter_bits - 1 downto 0) := (others => '0');
    signal clock_signal: std_logic;

    begin
    update_counter: process(clock_in)
    begin
    if clock_in'event and clock_in = '1' then
    if counter = max_counter then
    counter <= to_unsigned(0, counter_bits);
    clock_signal <= not clock_signal;
    else
    counter <= counter + 1;
    end if;
    end if;
    end process;

    clock_out <= clock_signal;
    end architecture rtl;


    --
    Frank Buss,
    http://www.frank-buss.de, http://www.it4-systems.de
     
    Frank Buss, Jul 28, 2006
    #3
  4. LRCR

    bm Guest

    Re: HELP. How to generate a single delayed pulse strobe in VHDL

    You should also add an entity to remove any metastability : a double Flip
    Flop on the input signal.

    signal my_sr : std_ulogic_vector(PIPELINE-1 downto 0)
    process(clk)
    sig_to_be_delayed_reg <= sig_to_be_delayed;
    sig_to_be_delayed_reg_reg <= sig_to_be_delayed_reg;
    my_sr <= my_sr(PIPELINE-2 downto 0) & sig_to_be_delayed_reg_reg;
    end process;
    delayed_sig<= my_sr(PIPELINE-1);


    "Frank Buss" <> wrote in message
    news:13wndprrnevhk.ltgooprepj2g$...
    > Thomas Stanka wrote:
    >
    >> signal my_sr : std_ulogic_vector(PIPELINE-1 downto 0)
    >> process(clk)
    >> my_sr <= my_sr(PIPELINE-2 downto 0) & sig_to_be_delayed;
    >> end process;
    >> delayed_sig<= my_sr(PIPELINE-1);

    >
    > With "process(clk)" you specify the sensitivity list, only, so it might
    > run
    > in a simulator, but not when synthesized, because the shift runs unclocked
    > with maximum speed, which depends on the part, temperature etc.
    >
    > I've designed it as a reusable entity:
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.NUMERIC_STD.ALL;
    >
    > entity shifter is
    > generic(pipeline_length: integer);
    > port(
    > clock: in std_logic;
    > data_in: in std_logic;
    > data_out: out std_logic);
    > end entity shifter;
    >
    > architecture rtl of shifter is
    > signal shift_register: unsigned(pipeline_length downto 0);
    >
    > begin
    > shift: process(clock)
    > begin
    > if clock'event and clock = '1' then
    > shift_register <= shift_register sll 1;
    > shift_register(0) <= data_in;
    > end if;
    > end process;
    >
    > data_out <= shift_register(shift_register'left);
    > end architecture rtl;
    >
    >
    > For testing on my Spartan 3E kit, I've used it like this:
    >
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.NUMERIC_STD.ALL;
    >
    > entity test is
    > port(
    > clk_50mhz: in std_logic;
    > btn_south: in std_logic;
    > led: out unsigned(7 downto 0));
    > end entity test;
    >
    > architecture rtl of test is
    > constant system_speed: natural := 50e6;
    >
    > signal clock_10hz: std_logic;
    > signal shift_register: unsigned(10 downto 0) := (others => '0');
    >
    > begin
    > clock_10hz_generator: entity clock_generator
    > generic map(clock_in_speed => system_speed, clock_out_speed => 10)
    > port map(
    > clock_in => clk_50mhz,
    > clock_out => clock_10hz);
    >
    > shifter_10_bits: entity shifter
    > generic map(pipeline_length => 10)
    > port map(
    > clock => clock_10hz,
    > data_in => btn_south,
    > data_out => led(0));
    >
    > led(1) <= btn_south;
    > led(2) <= clock_10hz;
    > led(7 downto 3) <= (others => '0');
    >
    > end architecture rtl;
    >
    >
    >
    > With this general usable clock divider:
    >
    >
    >
    > entity clock_generator is
    > generic(clock_in_speed, clock_out_speed: integer);
    > port(
    > clock_in: in std_logic;
    > clock_out: out std_logic);
    > end entity clock_generator;
    >
    > architecture rtl of clock_generator is
    >
    > function num_bits(n: natural) return natural is
    > begin
    > if n > 0 then
    > return 1 + num_bits(n / 2);
    > else
    > return 1;
    > end if;
    > end num_bits;
    >
    > constant max_counter: natural := clock_in_speed / clock_out_speed / 2;
    > constant counter_bits: natural := num_bits(max_counter);
    >
    > signal counter: unsigned(counter_bits - 1 downto 0) := (others => '0');
    > signal clock_signal: std_logic;
    >
    > begin
    > update_counter: process(clock_in)
    > begin
    > if clock_in'event and clock_in = '1' then
    > if counter = max_counter then
    > counter <= to_unsigned(0, counter_bits);
    > clock_signal <= not clock_signal;
    > else
    > counter <= counter + 1;
    > end if;
    > end if;
    > end process;
    >
    > clock_out <= clock_signal;
    > end architecture rtl;
    >
    >
    > --
    > Frank Buss,
    > http://www.frank-buss.de, http://www.it4-systems.de
     
    bm, Jul 30, 2006
    #4
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