help in VHDL procedure programming

Discussion in 'VHDL' started by VIPS, Feb 4, 2009.

  1. VIPS

    VIPS Guest

    Hi All

    i am trying to write a procedure in VHDL which i want to generate
    clock and on the rising edge of the clock i want to shift data on the
    rising edge .

    When i use the clause Rising_edge(clk) it is not doing anything and no
    output is seen ..

    Can anyone help as how to generate a clock inside the procedure and
    then shift data on that clock.

    I want the output of the procedure to give serial data on its
    generated clock

    Thanks in advance

    Vipul
     
    VIPS, Feb 4, 2009
    #1
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  2. VIPS

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    Procedure Clock

    rising_edge(clk) does not generate a clock, but rather detects the rising edge of the signal "clk". An example of its use:

    dff : process(clk)
    begin
    if rising_edge(clk) then
    q <= d;
    end if;
    end process;

    q and d are signals declared elswhere.

    Creating a synthesizable clock signal in a process is not something I would recommend. The clock timing would be difficult to control. Typically, a clock signal is generated by an external crystal oscillator.

    Generating a clock signal for simulation is another matter.


    clk_gen: process
    begin
    if not end_sim then
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
    else
    wait;
    end if;
    end process;

    The reason for using the boolean signal end_sim is to stop the clk_gen process when the simulation is ended; otherwise the process will keep running and the simulation will not end;

    I hope this helps.
     
    eliascm, Feb 5, 2009
    #2
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  3. VIPS

    Enes Erdin Guest

    On 4 ÂȘubat, 14:23, VIPS <> wrote:
    > Hi All
    >
    > i am trying to write a procedure in VHDL which i want to generate
    > clock and on the rising edge of the clock i want to shift data on the
    > rising edge .
    >
    > When i use the clause Rising_edge(clk) it is not doing anything and no
    > output is seen ..
    >
    > Can anyone help as how to generate a clock inside the procedure and
    > then shift data on that clock.
    >
    > I want the output of the procedure to give serial data on its
    > generated clock
    >
    > Thanks in advance
    >
    > Vipul


    Hi,

    You have to indicate for which purpose you will use this procedure.
    For testbench or for synthesis.

    For synthesis you can not generate clocks internally as you think. You
    must connect a clock pin or again generate a clock from a PLL by
    connecting a "real" clock.

    --enes
     
    Enes Erdin, Feb 5, 2009
    #3
  4. VIPS wrote:

    > i am trying to write a procedure in VHDL which i want to generate
    > clock and on the rising edge of the clock i want to shift data on the
    > rising edge .


    If I want to drive a port or signal, I need
    an architecture containing a parallel statement or a process.
    A process contains one or more sequential statements.

    A procedure could be called by this process to
    provide sequential statements, but a procedure
    alone cannot drive a port or signal.

    For a related example, see the process tb_clk here:
    http://mysite.verizon.net/miketreseler/test_uart.vhd
    Notice that this process calls the procedure fixed_stim
    to supply supply sequential statements for counting
    and stimulus generation.

    -- Mike Treseler
     
    Mike Treseler, Feb 5, 2009
    #4
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