Help in writing synthesizable code??

Discussion in 'VHDL' started by dcreddy1980, Dec 16, 2004.

  1. dcreddy1980

    dcreddy1980 Guest

    entity test is
    port(X : in std_logic;
    clk : in std_logic;
    Y : out std_logic);
    end test;

    architecture behaviour of test is
    signal tmp : integer :=3;
    constant clock period : time := 2 ns;
    begin
    Y <= X after tmp * clock period; -- "X after 6 ns"
    end behaviour;

    can body give me some ideas in synthesizing the above code...especially i
    want to remove the statement "X after tmp*clock period".

    Regards,
    chaitanya
    dcreddy1980, Dec 16, 2004
    #1
    1. Advertising

  2. dcreddy1980 a écrit:
    > entity test is
    > port(X : in std_logic;
    > clk : in std_logic;
    > Y : out std_logic);
    > end test;
    >
    > architecture behaviour of test is
    > signal tmp : integer :=3;
    > constant clock period : time := 2 ns;
    > begin
    > Y <= X after tmp * clock period; -- "X after 6 ns"
    > end behaviour;
    >
    > can body give me some ideas in synthesizing the above code...especially i
    > want to remove the statement "X after tmp*clock period".


    'after' clause is not synthesizable.
    If you want to delay your input signal by a number of clock periods, you
    have to use a delay chain:

    architecture rtl of test is
    constant tmp : natural := 3;
    begin
    process (clk)
    variable chain : std_logic_vector(tmp - 1 downto 0);
    begin
    if rising_edge(clk) then
    chain := chain(chain'left - 1 downto 0) & X;
    Y <= chain(chain'left);
    end if;
    end process;
    end rtl;

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
    Nicolas Matringe, Dec 16, 2004
    #2
    1. Advertising

  3. dcreddy1980

    bxbxb3 Guest

    u can also use state machines with no. of states=6. assign y<=x in state 6
    and y<=y for the rest of states.
    bxbxb3, Dec 18, 2004
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Saeed Nari

    GL85 synthesizable code

    Saeed Nari, Jul 25, 2003, in forum: VHDL
    Replies:
    2
    Views:
    1,485
    Antti Lukats
    Jul 28, 2003
  2. Stanley
    Replies:
    2
    Views:
    1,665
    Jim Lewis
    Dec 7, 2004
  3. Stefan Oedenkoven
    Replies:
    1
    Views:
    514
    zinga
    Jan 4, 2005
  4. Replies:
    8
    Views:
    973
    Mike Treseler
    Jul 26, 2005
  5. Rama
    Replies:
    7
    Views:
    514
Loading...

Share This Page