Help me with output TEXTIO please?

Discussion in 'VHDL' started by RobertBon, Oct 30, 2006.

  1. RobertBon

    RobertBon

    Joined:
    Oct 30, 2006
    Messages:
    4
    Hi all,

    Im new in the VHDL programming so i could use your help.
    My problem is about exporting results from my test bench to a .txt file.

    I made a testbench for a cordic core, this core gives me the cosine and sine results from a input angle. I generate this angle in a procedure in my testbench.
    I would like to write these results to a .txt file but i dont know how to do this.

    I have the following code:

    ----------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use std.textio.all;

    ENTITY testbench IS END;

    ARCHITECTURE full OF testbench IS

    component sc_corproc is
    port(
    clk : in std_logic;
    ena : in std_logic;
    Ain : in signed(15 downto 0);

    sin : out signed(15 downto 0);
    cos : out signed(15 downto 0));
    end component sc_corproc;

    constant clk_period : time := 9.259 ns;
    SIGNAL tb_ena : std_logic := '1';
    SIGNAL tb_clk : std_logic;
    SIGNAL x : integer;
    SIGNAL tb_Ain, tb_sin, tb_cos : signed(15 downto 0);

    BEGIN

    DUT : sc_corproc
    PORT MAP( clk => tb_clk,
    ena => tb_ena,
    Ain => tb_Ain,
    sin => tb_sin,
    cos => tb_cos
    );

    CLOCK : PROCESS
    BEGIN
    loop
    wait for clk_period/2;
    tb_clk <= '1';
    wait for clk_period/2;
    tb_clk <= '0';
    end loop;

    END PROCESS;

    OUTPUT_RESULTS : process

    File dataout : TEXT is out "output.txt";
    variable temp : signed(15 downto 0);
    VARIABLE line_out : LINE;

    begin
    wait until tb_clk'event and tb_clk='1';

    if tb_clk'event and tb_clk='1'then
    temp(15 downto 0) := tb_sin(15 downto 0);

    write(line_out, temp);
    writeline(dataout, line_out);

    else
    wait until tb_clk'event and tb_clk='1';
    end if;
    end process;

    MAIN: PROCESS(tb_clk)
    VARIABLE K : INTEGER := 0;
    CONSTANT N : INTEGER := 120;

    PROCEDURE ANGLE_GEN(SIGNAL CLOCK : IN STD_LOGIC)IS

    BEGIN
    if rising_edge(tb_clk) then

    K := K + 5;
    x <= 65536 * K/N;
    tb_Ain <= CONV_SIGNED(x,16);

    end if;
    END PROCEDURE ANGLE_GEN;

    BEGIN

    ANGLE_GEN(tb_clk);

    END PROCESS MAIN;

    END full;

    -----------------------------------------------------

    When i try to compile it with MODELSIM i get the error that there are no feasible entries for the subprogram write.

    I think this is because the testbench first needs to generate an angle for the core and than the results are given back. But with compiling, there's no angle input because it is made during simulation so there's no result yet to write it to my .txt file.

    I hope there's someone who has the time to help me with this problem.
    Kind Regards,

    Robert B.

    p.s. pls keep in notice that i'm new to the VHDL scene.
     
    RobertBon, Oct 30, 2006
    #1
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