# help need in the Radix 4 algorithm of 64 point.

Discussion in 'VHDL' started by senthil, Feb 14, 2004.

1. ### senthilGuest

hello friends,

w.r.t the design of fft/ifft in vhdl, there are several algorithms,
here, i go for radix 4 algorithm,
formulae behind the radix 4 DIF ifft

y(l) = x(l) + x(l+N/2) + x(l+N/4) + x(l+3N/4);
z(l) = (x(l) - x(l+N/2)+j(x(l+N/4) - x(l+3N/4))Wl;
g(l) = (x(l) + x(l+N/2) - x(l+N/4) - x(l+3N/4))W2l;
h(l) = (x(l) - x(l+N/2)-j(x(l+N/4) - x(l+3N/4))W3l;
where Wl- twiddle factor.

below mentioned the first stage of 64 point ifft using radix 4
formulae..
for l in 0 to 15
-- 64 to 16 point l varies frm 0 to 15 stage 1
yre(l) <= modre(l)+modre(l+32)+modre(l+16)+modre(l+48);
yim(l) <= modim(l)+modim(l+32)+modim(l+16)+modim(l+48);

yre(l+16) <= (modre(l) - modre(l+32) - modim(l+16) +
modim(l+48))*stg1revalue(l) - (modim(l) - modim(l+32) + modre(l+16) -
modre(l+48))*stg1imvalue(l);
yim(l+16) <= (modre(l) - modre(l+32) - modim(l+16) +
modim(l+48))*stg1imvalue(l) + (modim(l) - modim(l+32) + modre(l+16) -
modre(l+48))*stg1revalue(l);

yre(l+32) <= (-modre(l+16) - modre(l+48) + modre(l) +
modre(l+32))*stg1revalue(2*l) - (-modim(l+16) - modim(l+48) + modim(l)
+ modim(l+32))*stg1imvalue(2*l);
yim(l+32) <= (-modre(l+16) - modre(l+48) + modre(l) +
modre(l+32))*stg1imvalue(2*l) + (-modim(l+16) - modim(l+48) + modim(l)
+ modim(l+32))*stg1revalue(2*l);

yre(l+48) <= (modim(l+16) - modim(l+48) + modre(l) -
modre(l+32))*stg1revalue(3*l) - (-modre(l+16) + modre(l+48) + modim(l)
- modim(l+32))*stg1imvalue(3*l);
yim(l+48) <= (modim(l+16) - modim(l+48) + modre(l) -
modre(l+32))*stg1imvalue(3*l) + (-modre(l+16) + modre(l+48) + modim(l)
- modim(l+32))*stg1revalue(3*l);

end loop

where the stg1revalue is look up table where i store the cos and sine
values directly.
and modre, modim are the input to the first stage and it will have
modre(0 to 63) and modim(0 to 63)..
after i getting 4 16 values , i go to 16 point one in that i got 4 4
point and then i finally go to 4 point.

my question is, is this contribution to my 64 point is correct for the
first stage or not?
or pls give any suggestion regarding that and also give another way of
approaching ..

senthil.R

senthil, Feb 14, 2004

2. ### deepak_ddnGuest

Hello all,

I too am looking for the ways to implement 64 point IFFT and FFT in VHDL. I saw Ist stage implementation . Could anyone describe me full implementation and the corresponding sine and cosine values.

Deepak

deepak_ddn, Feb 19, 2004

3. ### Michael GallenGuest

Hello Deepak,

We have an app. Tyd-IP Code Generator which will give you FFT / IFFT (real
and complex) VHDL...all synthesizable and easily readable with full
comments. It also gives you testbenchs, test data, and simulator compile
macros. Anything else you require ?

Michael
www.tyder.com

"deepak_ddn" <> wrote in message
news:...
> Hello all,
>
> I too am looking for the ways to implement 64 point IFFT and FFT in VHDL.

I saw Ist stage implementation . Could anyone describe me full
implementation and the corresponding sine and cosine values.
>
> Deepak
>

Michael Gallen, Feb 21, 2004

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