help on an array problem

Discussion in 'VHDL' started by hongyan, Apr 5, 2005.

  1. hongyan

    hongyan Guest

    The following is my source code;
    -----------------------------------------------------------
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

    entity EGC is
    generic(M : natural := 4);
    Port ( input1 : in std_logic_vector(15 downto 0);
    output1 : out std_logic_vector(15 downto 0));

    end EGC;

    architecture Behavioral of EGC is
    subtype vector16 is std_logic_vector(15 downto 0);
    type vector_M_16_Out is array(0 to M) of vector16;
    signal out1: vector_M_16_Out;


    begin

    out1(0) <= input1;

    proc0 : process(out1, input1)
    begin
    --out1(0) <= input1;
    for i in 1 to M loop
    out1(i) <= 2+out1(i-1);
    end loop;
    end process proc0;

    output1 <= out1(M);
    end Behavioral;
    -----------------------------------------------

    It is very strange that it doesn't work this way. All the signals
    out1(0-4) are xxxx. But if I put "out1(0) <= input1;" into the
    process, it works fine.
    I can't understand this because the for loop in the process won't
    modify the out1(0). Did I miss somthing? Any suggestions will be
    appreciate.

    For your convience, here is my test file and .do file:
    test file
    -----------------------------------------------
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;

    ------------------------entity Declaration----------------------------
    entity test_EGC is
    end test_EGC;

    ------------------------ Architecture Declaration
    ----------------------

    architecture test_EGC of test_EGC is

    signal output1, input1: std_logic_vector(15 downto 0);

    component EGC
    generic(M : natural := 4);
    Port ( input1 : in std_logic_vector(15 downto 0);
    output1 : out std_logic_vector(15 downto 0));

    end component;

    begin

    proc_input1 : process is
    begin
    input1 <= X"0001";
    wait for 60 ns;
    input1 <= X"0000";
    wait;
    end process proc_input1; --proc_reset : process is

    U_EGC : EGC
    generic map(M=>4)
    port map
    ( input1 => input1, output1 => output1);

    end test_EGC;
    -----------------------------------------------------
    ..do file
    ---------------------------------------------------
    vsim work.test_EGC
    view wave
    add wave sim:/test_egc/output1
    add wave sim:/test_egc/input1
    add wave sim:/test_egc/u_egc/out1

    run 500ns
    --------------------------------------------------

    Thank you,
    Hongyan
     
    hongyan, Apr 5, 2005
    #1
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  2. "hongyan" <> wrote in message
    news:...
    > The following is my source code;
    > -----------------------------------------------------------
    > library IEEE;
    > use IEEE.std_logic_1164.all;
    > use IEEE.std_logic_arith.all;
    > use IEEE.std_logic_unsigned.all;
    >
    > entity EGC is
    > generic(M : natural := 4);
    > Port ( input1 : in std_logic_vector(15 downto 0);
    > output1 : out std_logic_vector(15 downto 0));
    >
    > end EGC;
    >
    > architecture Behavioral of EGC is
    > subtype vector16 is std_logic_vector(15 downto 0);
    > type vector_M_16_Out is array(0 to M) of vector16;
    > signal out1: vector_M_16_Out;
    >
    >
    > begin
    >
    > out1(0) <= input1;
    >
    > proc0 : process(out1, input1)
    > begin
    > --out1(0) <= input1;
    > for i in 1 to M loop
    > out1(i) <= 2+out1(i-1);
    > end loop;
    > end process proc0;
    >
    > output1 <= out1(M);
    > end Behavioral;
    > -----------------------------------------------
    >
    > It is very strange that it doesn't work this way. All the signals
    > out1(0-4) are xxxx. But if I put "out1(0) <= input1;" into the
    > process, it works fine.
    > I can't understand this because the for loop in the process won't
    > modify the out1(0). Did I miss somthing? Any suggestions will be
    > appreciate.
    >

    <snip>

    I don't think Out1 should be in your process sensitivity list.
    Everytime input1 changes proc0 is run, and at the same time Out0 is
    undefined as although the inputs have been set, the outputs haven't been
    assigned yet. Thus all the additions in the process are undefined, and will
    generate Xs.

    With the statement inside the process, Out1(0) is defined at the end of the
    first iteration, and since you have Out1 in your process sensitivity list
    the process will repeat until the additions have propagated to Out1(M) and
    Out1 no longer changes.

    Instead try:

    out1(0) <= input1;

    gen0:
    for i in 1 to M generate
    out1(i) <= 2+out1(i-1);
    end generate;

    output1 <= out1(M);

    which to me seems more elegant.

    Someone correct me if I'm wrong - I've only started coding vhdl (since uni)
    last week. :)

    Ross
     
    Ross Marchant, Apr 5, 2005
    #2
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  3. hongyan

    Neo Guest

    I think this is more to do with how the simulator is assigning drivers
    for the declared signals than with event scheduling. actually it should
    work without problems as, an event on out1(0) should trigger the
    process again. the input1 in the sensitivity list is unnecessary as
    none of the assignments inside the process depend on it. but strangely
    the out1(0) appears not to be driven at all.
     
    Neo, Apr 5, 2005
    #3
  4. hongyan

    hongyan Guest

    Thanks Neo. right, input1 in the sensitivity list is unnecessary.
    And thanks for Ross, I know there are some other ways can solve the
    problem. But I just wondering what cause the problem in my coding.
     
    hongyan, Apr 6, 2005
    #4
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