Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.all;
Entity cpu is
port( R0, R1, R2, R3, R4, R5, R6, R7: in std_logic_vector(7 downto 0);
IR: in std_logic_vector(12 downto 0);
CLK: in std_logic;
output: out std_logic_vector(7 downto 0));
end cpu;
Architecture cpu of cpu is
signal BusA, BusB: std_logic_vector(7 downto 0);
signal SA: std_logic_vector(2 downto 0);
signal SB: std_logic_vector(2 downto 0);
signal SD: std_logic_vector(2 downto 0);
signal OP: std_logic_vector(3 downto 0);
type Regs is array(0 to 7) of std_logic_vector(7 downto 0);
signal Reg: Regs;
signal Result: std_logic_vector(7 downto 0);
Begin
SA <= IR(12 downto 10);
SB <= IR(9 downto 7);
SD <= IR(6 downto 4);
OP <= IR(3 downto 0);
process(CLK)
begin
if(rising_edge(CLK)) then
Reg(0) <= R0;
Reg(1) <= R1;
Reg(2) <= R2;
Reg(3) <= R3;
Reg(4) <= R4;
Reg(5) <= R5;
Reg(6) <= R6;
Reg(7) <= R7;
end if;
end process;
-------------------------------------------
BusA <= Reg(0) when SA = "000" else
Reg(1) when SA = "001" else
Reg(2) when SA = "010" else
Reg(3) when SA = "011" else
Reg(4) when SA = "100" else
Reg(5) when SA = "101" else
Reg(6) when SA = "110" else
Reg(7);
-------------------------------------------
BusB <= Reg(0) when SB = "000" else
Reg(1) when SB = "001" else
Reg(2) when SB = "010" else
Reg(3) when SB = "011" else
Reg(4) when SB = "100" else
Reg(5) when SB = "101" else
Reg(6) when SB = "110" else
Reg(7);
--------------------------------------------
Result <= BusA + BusB when OP = "0000" else
BusA - BusB when OP = "0010" else
BusA XOR BusB when OP = "0011" else
'0' & BusA(7 downto 1) when OP = "0100" else
BusA(6 downto 0) & '0' when OP = "0101" else
BusA(0) & BusA(7 downto 1) when OP = "1010" else
BusA + BusB;
--------------------------------------------
output <= Result;
process(CLK)
begin
if(Falling_edge(CLK)) then
Reg(conv_integer(SD)) <= Result;
end if;
end process;
end cpu;