help on coding pls~

Discussion in 'VHDL' started by leon86, May 3, 2006.

  1. leon86

    leon86 Guest

    A device reads in a 4 bits input. Example '0001'. Then for '0001' it will
    activate the timer for 30 minutes and start to count down until it reaches
    0 min. After that is will output a '00'. I have a crystal oscillator with
    1Mhz frequency.


    I having problem on how to write the code for the timer to be set at 30
    min in VHDL and then start to count down with the 1Mhz frequency.


    Someone pls help me~~

    Thanks
    leon86, May 3, 2006
    #1
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  2. leon86

    backhus Guest

    Hi Leon,
    what's so difficult in dividing 30 min by 1 ┬Ás (Period time of 1MHz)?
    Then you have a number to count to.

    Of course you can not use time units to build a counter.

    time <= time + 1 us; -- does not work for synthesis!


    have a nice synthesis

    Eilert

    leon86 schrieb:
    > A device reads in a 4 bits input. Example '0001'. Then for '0001' it will
    > activate the timer for 30 minutes and start to count down until it reaches
    > 0 min. After that is will output a '00'. I have a crystal oscillator with
    > 1Mhz frequency.
    >
    >
    > I having problem on how to write the code for the timer to be set at 30
    > min in VHDL and then start to count down with the 1Mhz frequency.
    >
    >
    > Someone pls help me~~
    >
    > Thanks
    >
    backhus, May 4, 2006
    #2
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  3. leon86

    Jeremy Ralph Guest

    Perhaps something like this...

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;

    ENTITY countdown IS
    PORT(
    clk : IN STD_LOGIC;
    rstb : IN STD_LOGIC; -- active low async reset
    activation : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    the_output : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
    );
    END countdown;

    ARCHITECTURE rtl OF countdown IS
    CONSTANT ACTIVATION_CODE : STD_LOGIC_VECTOR(activation'RANGE) :=
    "0001";
    CONSTANT CYCLES_PER_SEC : natural := 10**6;
    CONSTANT COUNTDOWN_LOAD : natural := CYCLES_PER_SEC * 60 * 30 - 1;
    SIGNAL the_output_r : std_logic_vector(1 DOWNTO 0);
    SIGNAL countdown_r : natural RANGE 0 TO COUNTDOWN_LOAD-1;
    SIGNAL counting_r : boolean;
    BEGIN

    the_output <= the_output_r;

    countdown_proc: PROCESS(clk,rstb)
    BEGIN
    IF rstb = '0' THEN
    the_output_r <= (OTHERS => '1');
    countdown_r <= COUNTDOWN_LOAD-1;
    counting_r <= FALSE;
    ELSIF clk'event AND clk = '1' THEN
    IF (counting_r) THEN
    IF (countdown_r = 0) THEN
    -- countdown hit zero
    counting_r <= FALSE;
    countdown_r <= COUNTDOWN_LOAD-1;
    the_output_r <= (OTHERS => '0');
    ELSE
    countdown_r <= countdown_r - 1;
    the_output_r <= (OTHERS => '1');
    END IF;
    ELSE
    IF activation = ACTIVATION_CODE THEN
    counting_r <= TRUE;
    END IF;
    END IF;
    END IF;
    END PROCESS countdown_proc;

    END rtl;

    ---
    PDTi [ http://www.productive-eda.com ]
    SpectaReg -- Spec-down code and doc generation for register maps
    Jeremy Ralph, May 4, 2006
    #3
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