help please! 4bit adder/sub

[Sam Aborhey]

can you tell me whats wrong with this? and please help me fix it - it doesnt
compile and i need it urgently

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY adder4 IS
PORT ( Cin :IN STD_LOGIC;
X,Y :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Cout, Overflow :OUT STD_LOGIC;
A,B,C,D :OUT STD_LOGIC);

END adder4;

ARCHITECTURE Behavior OF adder4 is
SIGNAL Sum: STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
SUM <= ('0' & X) OR (Y XOR Cin) OR Cin;
S <= Sum(3 DOWNTO 0);
Cout <= Sum(4);
A <= NOT Sum(2) AND (Sum(0) OR Sum(1));
B <= Sum(0)AND NOT Sum(2);
C <= (Sum(0)AND NOT Sum(2))OR (Sum(0)AND SUM(1))OR (Sum(2)AND NOT Sum(1)AND
NOT Sum(0));
D <= (Sum(2));
Overflow <=Sum(4) XOR X(3) XOR Y(3) XOR Sum(3);
END Behavior;

 

[Paul Uiterlinden]

can you tell me whats wrong with this? and please help me fix it -
it doesnt compile and i need it urgently

Yeah, on monday, right?
I'm not going to do your homework, only give a few hints:

1) You say it does not compile, so there's an error message. Read it
carefully, it tells you what's wrong.

2) Why are you using ieee.std_logic_unsigned.all? It's not needed,
you're not using any arithmetic functions with type unsigned. And if
you where, use ieee.numeric_std instead (it is IEEE standardized,
std_logic_unsigned is not).

3) The terms of the right hand side of the assignment of SUM are of
unequal length. You're even mixing single bits and vectors.

Paul.

 

[Sam Aborhey]

Yeah, on monday, right?
I'm not going to do your homework, only give a few hints:

1) You say it does not compile, so there's an error message. Read it
carefully, it tells you what's wrong.

2) Why are you using ieee.std_logic_unsigned.all? It's not needed,
you're not using any arithmetic functions with type unsigned. And if
you where, use ieee.numeric_std instead (it is IEEE standardized,
std_logic_unsigned is not).

3) The terms of the right hand side of the assignment of SUM are of
unequal length. You're even mixing single bits and vectors.

For the first two - that is what we were told to use. for the third one, i
know Cin is 1 bit and Y is 4 bits. but i have no idea how to make this
work - because i need cin to be 1 bit. is there a way i can make cin 4 bits
for just that part?

ps.........thast where i'm going wrong right? i'm pretty new to vhdl so i'm
having trouble with the coding

 

[Jim Lewis]

Sam,
Writing VHDL code the way you have misses the point
of VHDL being a higher level language. You really
want to be doing adds using the overloaded functions
in the package your were told to use (std_logic_unsigned).
Note some of the advice you get will reflect the fact
that some don't like using this package. In fact for
your usage, I recommend using the package numeric_std
and the type unsigned, however, being in college, you
have to do some things the way the professor recommends -
even if it is a bad design practice.

The issue the problem you have is designed to illustrate
is the fact that when you add two four bit numbers you
always get a 4 bit result. Your job is to figure out
how to extend them to get a result of the proper size.

One question I have for you, is it ever possible to
get an overflow when adding two unsigned numbers?
This is not a VHDL question - this is a question of
looking at the possible range of values in X and Y and
accessing whether it is possible.

If you need more hints see the following paper on our
website:
VHDL Math Tricks of the Trade

Cheers,
Jim Lewis
P.S.
In fact, if you want to do homework in a more widely
industry approved manner, keep the port types std_logic_vector,
but internal to your design make the types unsigned
and use the package ieee.numeric_std:
use ieee.numeric_std.all ;

The above paper has everything you need to solve your
problem this way.
--
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Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
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