Help to a generic OR-gate

[westkite]

Hey

I hope some of you can help me.

I like to generate a OR-gate with a generic numbers of inputs. How do you do that in VHDL?

What I have is ex. a signal X std_logic_vector(i downto 0) and I like to or all the "single bits" together.
Y <= X(i) or X(i-1) downto null.

But I don't know how do do that generically!

Many thanks for your help.
Thomas

 

[westkite]

Well

After a little messing around. I came up with a solution. I don't like because it uses adders instead of OR-gates. But it is implemented as Or-gates, so I guess it is okay!
Here is the code:

entity ORGate is
Generic (Channels : natural := 6);
Port (
Data_IN : in STD_LOGIC_VECTOR (Channels downto 0);
Or_OUT : out STD_LOGIC);
end ORGate;

architecture Behavioral of ORGate is

begin

process (Data_IN)
variable sum : std_logic_vector(Channels downto 0);
begin
sum := (others => '0');
for i in 0 to Channels loop
sum := sum + Data_IN(i);
end loop;

if (sum > CONV_STD_LOGIC_VECTOR(0, Channels+1)) then
Or_OUT <= '1';
else
Or_OUT <= '0';
end if;
end process;


People are free to use this...