help to input array

Discussion in 'VHDL' started by ashu, Jan 12, 2006.

  1. ashu

    ashu Guest

    hi friends
    i have written a program to search a no. in an arrray & get the result
    in form of apulse going high or low,but
    given no is compared with only the last value & desired output is not
    coming.
    my basic problem is to input an array directly to input port.also if
    somebody can give some example program or tips about reading & writing
    files in vhdl. i m using modelsim.
    i have written the code & test bench for the code for refrene.
    thanks
    ashwani anand

    library ieee ;
    use ieee.std_logic_1164.all ;
    package my is
    type arec is array (0 to 49 ) of integer range 0 to 50 ;
    type inst is record
    ary : arec ;

    end record ;
    end my ;

    library ieee ;
    use ieee.std_logic_1164.all ;
    use work.my .all ;

    entity rec is

    port( a : in inst ;
    b : in integer range 0 to 55 ;
    o : out std_logic );
    end rec ;

    architecture a of rec is
    begin
    process (a,b)

    -- variable q : integer range 0 to 55 ;
    -- variable p : integer range 0 to 50 ;

    begin


    for i in 0 to 49 loop

    -- p := b ;

    --q := a.ary(i) ;

    if (b = a.ary(i)) then

    o <= '1' ;

    else

    o <= '0' ;

    end if ;
    end loop ;
    end process ;
    end a ;

    --TEST BENCH


    library ieee ;
    use ieee.std_logic_1164.all ;

    package my is
    type arec is array (0 to 49 ) of integer range 0 to 50 ;
    type inst is record
    ary : arec ;

    end record ;
    end my ;

    library ieee ;
    use ieee.std_logic_1164.all ;
    use work.my .all ;

    entity tb_rec is
    end ;

    architecture a of tb_rec is


    component rec

    port ( a : in inst ;
    b : in integer range 0 to 50 ;
    o : out std_logic );

    end component ;

    signal o : std_logic ;
    signal a : inst ;
    signal b : integer range 0 to 55 ;

    begin

    U1 : rec port map (a =>a,b =>b , o =>o );

    process

    variable t : integer range 0 to 55;
    variable q : integer range 0 to 55;
    begin

    wait for 10 ns ;
    b <= 50 ;
    wait for 10 ns ;


    t := 1 ;

    for i in 0 to 49 loop

    a.ary(i) <= t ;

    t := t + 1 ;

    if (t = 51 ) then

    t := 0 ;
    wait for 10 ns ;
    b <= 52 ;
    wait for 10 ns ;

    wait for 10 ns ;
    b <= 23 ;
    wait for 10 ns ;

    end if ;
    end loop ;


    end process ;

    end a;

    result of this program is a pulse high for 23 & 50 low for 52 but it is
    remaning high for 50 only which is last value stored in array.
    ashu, Jan 12, 2006
    #1
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  2. ashu

    jens Guest

    The lack of formatting makes it very difficult to read, but it appears
    as if the problem comes from the fact that the last signal assignment
    in a process wins, so o can only be '1' when b = a.ary(49).

    Using a default signal assigment might work...

    o <= '0' ;

    for i in 0 to 49 loop
    if (b = a.ary(i)) then
    o <= '1' ;
    end if ;
    end loop ;

    This assumes that a parallel comparison is what is desired, and
    hopefully there's a clock outside of this process somewhere that is
    clocking the inputs and outputs of this process.
    jens, Jan 12, 2006
    #2
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