Help! VHDL analysis on quartus II won't work, 3 errors

[mangoflango]

So this is my first assignment with VHDL, so its super duper new, and even though it's simple Quartus keeps giving me this error that says "Analysis was NOT successful (3 errors)"
I can't figure out what's wrong. Here's my code

entity ABCD is
port (
A : in bit;
B : in bit;
C : in bit;
D : in bit;
F : out bit;
);
end entity ABCD;

architecture DATAFLOW of ABCD is
begin
with A&B&C&D select
F<= '1' when B"0000",
'1' when B"0001",
'1' when B"1000",
'1' when B"1001",
'1' when B"1010",
'1' when B"1011",
'1' when B"1110",
'1' when B"1111",
'0' when others;
end architecture DATAFLOW

 

[joris]

This should work better (it elaborates successfully -- not tested beyond that)

entity ABCD is
port (
A : in bit;
B : in bit;
C : in bit;
D : in bit;
F : out bit
);
end entity ABCD;

architecture DATAFLOW of ABCD is
  signal sel : bit_vector(3 downto 0);
begin
  sel <= A&B&C&D;
with sel select
F<= '1' when B"0000",
'1' when B"0001",
'1' when B"1000",
'1' when B"1001",
'1' when B"1010",
'1' when B"1011",
'1' when B"1110",
'1' when B"1111",
'0' when others;
end architecture DATAFLOW;

Perhaps the best thing to do is `diff` on your original file and this version -- it should be obvious what changed (and why)
You are not allowed to use an immediate value with select, so I store the value in a signal and use that one in the select statement.