fred said:
I disagree, a case is a decoder, the others term (the brackets were a
mistake btw) just fills in the empty slots, I see no latches.
Nope
I think this is misunderstanding. I tought that you were trying to code the
code like this:
process(clock) is
begin
if rising_edge(clock) then
case (state) is
when idle => ...
when writing =>
output_enable <= '1';
when reading => ...
when someOtherState => ...
when others =>
output_enable <= '0';
end case;
end if;
end process;
And you tought:
process(clock) is
begin
if rising_edge(clock) then
case (state) is
when writing =>
output_enable <= '1';
when others =>
output_enable <= '0';
end case;
end if;
end process;
The example is little too simple, because usually there is a huge pile of
signals inside the states. And then the others option is quite difficult
to use. But the default value option is easy to use.
From a real world hardware perspective I look upon this sort of thing as
multiple sources (even though in VHDL it is not) and so won't do it;
irrespective of whether tools 'know what I mean'.
Usually there are multiple sources to the combinatorial network. And the
style does not imply multiple drivers to same signal. The tools
know what you mean, because they must do that by definition (check how signal
assignment and delta cycle is defined).
And that default value style is used by designers very frequently. Usually
by the more experienced designers. I sit on top of hunders of thousands
of lines of VHDL code, made by a legion of VHDL coders. It's fun to check
sometimes how different styles coders have, but also there are some
commonalities. There are some styles that are dangerous in terms
of the whole tool flow, but this is not one of them.
In hardware, the signal does not set to one level and then change to
another one (or how ever many) deltas later so in that way simulation does
not follow hardware.
In real HW the signal value can jump around during it's propagation
trough the combinatorial logic, so it is not stable. It just has to
be stable around the clock edge to fullfill the setup and hold times.
That makes debugging of huge netlist quite painful, especially if the valid
window is small due to tight timing.
--Kim