Help with creating a very small CPU

Discussion in 'VHDL' started by TweedleDee, Feb 17, 2009.

  1. TweedleDee

    TweedleDee Guest

    Disclaimer: I'm fairly new to VHDL

    I am trying to do operations on my accumulator using different bits of
    the instruction register. For instance, bit 2 will clear A and bit 3
    will increment A. I want these operations to be able to happen in one
    cycle with one instruction in order (e.g. Clear A, then increment).
    This piece of code is what I came up with but it will only do one of
    the operations, not both. I could break these down into different
    clock cycles, but I'm hoping there is a way to do it in one. Any
    ideas?

    process (clk) begin
    if rising_edge (clk) then
    if en_execute = '1' then
    if IR(2) = '1' then --clear accumulator
    A <= "00000000";
    end if;

    if IR(3) = '1' then --increment accumulator
    A <= A + 1;
    end if;
    end if;
    end if;
    end process;
     
    TweedleDee, Feb 17, 2009
    #1
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  2. TweedleDee

    Guest

    On Feb 17, 3:19 pm, TweedleDee <> wrote:
    > Disclaimer: I'm fairly new to VHDL
    >
    > I am trying to do operations on my accumulator using different bits of
    > the instruction register.  For instance, bit 2 will clear A and bit 3
    > will increment A.  I want these operations to be able to happen in one
    > cycle with one instruction in order (e.g. Clear A, then increment).
    > This piece of code is what I came up with but it will only do one of
    > the operations, not both.  I could break these down into different
    > clock cycles, but I'm hoping there is a way to do it in one.  Any
    > ideas?
    >
    > process (clk) begin
    >     if rising_edge (clk) then
    >       if en_execute = '1' then
    >          if IR(2) = '1' then    --clear accumulator
    >             A <= "00000000";
    >          end if;
    >
    >          if IR(3) = '1' then    --increment accumulator
    >             A <= A + 1;
    >          end if;
    >       end if;
    >     end if;
    > end process;



    Variables can be used to hold intermediate results, so everything
    happens in one clock cycle:

    process (clk)
    variable tmpA : T; -- T is whatever type A is
    begin
    if rising_edge (clk) then
    if en_execute = '1' then
    tmpA := A; -- starting off fresh!
    if IR(2) = '1' then --clear accumulator
    tmpA <= "00000000"; -- use tmpA!
    end if;

    if IR(3) = '1' then --increment accumulator
    tmpA <= tmpA + 1; -- use tmpA!
    end if;
    A <= tmpA; -- all done!

    end if;
    end if;
    end process;

    Of course, if you want to dynamically change the order you'll need
    more bits and more complicated decoding.

    HTH,

    - Kenn
     
    , Feb 17, 2009
    #2
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  3. TweedleDee

    Guest

    On Feb 17, 3:26 pm, wrote:
    > On Feb 17, 3:19 pm, TweedleDee <> wrote:
    >
    >
    >
    > > Disclaimer: I'm fairly new to VHDL

    >
    > > I am trying to do operations on my accumulator using different bits of
    > > the instruction register.  For instance, bit 2 will clear A and bit 3
    > > will increment A.  I want these operations to be able to happen in one
    > > cycle with one instruction in order (e.g. Clear A, then increment).
    > > This piece of code is what I came up with but it will only do one of
    > > the operations, not both.  I could break these down into different
    > > clock cycles, but I'm hoping there is a way to do it in one.  Any
    > > ideas?

    >
    > > process (clk) begin
    > >     if rising_edge (clk) then
    > >       if en_execute = '1' then
    > >          if IR(2) = '1' then    --clear accumulator
    > >             A <= "00000000";
    > >          end if;

    >
    > >          if IR(3) = '1' then    --increment accumulator
    > >             A <= A + 1;
    > >          end if;
    > >       end if;
    > >     end if;
    > > end process;

    >
    > Variables can be used to hold intermediate results, so everything
    > happens in one clock cycle:
    >
    > process (clk)
    >   variable tmpA : T; -- T is whatever type A is
    > begin
    >      if rising_edge (clk) then
    >        if en_execute = '1' then
    >           tmpA := A; -- starting off fresh!
    >           if IR(2) = '1' then    --clear accumulator
    >              tmpA <= "00000000"; -- use tmpA!
    >           end if;
    >
    >           if IR(3) = '1' then    --increment accumulator
    >              tmpA <= tmpA + 1; -- use tmpA!
    >           end if;
    >         A <= tmpA; -- all done!
    >
    >        end if;
    >      end if;
    >  end process;
    >
    > Of course, if you want to dynamically change the order you'll need
    > more bits and more complicated decoding.
    >
    > HTH,
    >
    >  - Kenn


    Oops, forgot to finish the edits! Variables are always assigned using
    the ":=" instead of the "<=" operator, so change the above to read:

    tmpA := "00000000"; -- use tmpA!

    tmpA := tmpA + 1; -- use tmpA!


    - Kenn
     
    , Feb 17, 2009
    #3
  4. TweedleDee

    TweedleDee Guest

    Excellent! Thank you! I'll give a try.
     
    TweedleDee, Feb 17, 2009
    #4
  5. wrote:

    > if IR(2) = '1' then --clear accumulator
    > tmpA <= "00000000"; -- use tmpA!

    ^^ ^^^
    := assign

    > if IR(3) = '1' then --increment accumulator
    > tmpA <= tmpA + 1; -- use tmpA!

    ^^
    :=
     
    Mike Treseler, Feb 17, 2009
    #5
  6. TweedleDee wrote:
    > I am trying to do operations on my accumulator using different bits of
    > the instruction register. For instance, bit 2 will clear A and bit 3
    > will increment A. I want these operations to be able to happen in one
    > cycle with one instruction in order (e.g. Clear A, then increment).
    > This piece of code is what I came up with but it will only do one of
    > the operations, not both. I could break these down into different
    > clock cycles, but I'm hoping there is a way to do it in one. Any
    > ideas?
    >
    > process (clk) begin
    > if rising_edge (clk) then
    > if en_execute = '1' then
    > if IR(2) = '1' then --clear accumulator
    > A <= "00000000";
    > end if;
    >
    > if IR(3) = '1' then --increment accumulator
    > A <= A + 1;
    > end if;
    > end if;
    > end if;
    > end process;



    IF ir(2) = '1' AND ir(3) = '1' THEN
    a <= "00000001";
    ELSIF ir(2) = '1' THEN
    a <= "00000000";
    ELSIF ir(3) = '1' THEN
    a <= a + 1;
    END IF;

    or

    CASE ir(3 DOWNTO 2) IS
    WHEN "01" => a <= "00000000";
    WHEN "10" => a <= a + 1;
    WHEN "11" => a <= "00000001";
    WHEN OTHERS => NULL;
    END CASE;

    Kind regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Feb 19, 2009
    #6
  7. TweedleDee

    jacko Guest

    On 17 Feb, 20:19, TweedleDee <> wrote:
    > Disclaimer: I'm fairly new to VHDL
    >
    > I am trying to do operations on my accumulator using different bits of
    > the instruction register.  For instance, bit 2 will clear A and bit 3
    > will increment A.  I want these operations to be able to happen in one
    > cycle with one instruction in order (e.g. Clear A, then increment).
    > This piece of code is what I came up with but it will only do one of
    > the operations, not both.  I could break these down into different
    > clock cycles, but I'm hoping there is a way to do it in one.  Any
    > ideas?
    >
    > process (clk) begin
    >     if rising_edge (clk) then
    >       if en_execute = '1' then
    >          if IR(2) = '1' then    --clear accumulator
    >             A <= "00000000";
    >          end if;
    >
    >          if IR(3) = '1' then    --increment accumulator
    >             A <= A + 1;
    >          end if;
    >       end if;
    >     end if;
    > end process;


    Do bare in mind that such a thing may expand to many cascaded logic
    operations bypassed by a two way multiplexer, cascaded together. Such
    an arrangement may reduce the Fmax of the CPU significantly. A full
    expansion of the logic functions may lead to quite a large CPU, but
    faster. You may find a pipeline at each stage (or IR bit) keeps the
    size small (register in mux LUT cell), so no real extra logic appart
    from delay line for bits of IR. Significant differences in execution
    time of logic operations, can limit design Fmax to lowest speed of all
    ops. Making the slowest op take 2 pipeline clocks can often boost
    performance.

    cheers jacko

    http://nibz.googlecode.com VHDL microprocessor. *****<570 Altera
    LEs***** (16 bit), 20MHz in C5 grade MAXIIZ, 40 I/O pins (programmable
    direction), Clocked Counter...
     
    jacko, Feb 19, 2009
    #7
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