# help with incrementors

Discussion in 'VHDL' started by Lilmiss, Jul 19, 2005.

1. ### LilmissGuest

If anyone provide me with vhdl source code for any of the following:
1) Design a circuit that increments a 4-bit number A3A2A1A0 by 1. In a
similar manner to the adder circuit, start by designing a 1-bit
incrementer circuit.
2)Write a behavioral-style VHDL code for a 1-bit incrementor circuit as
described in Problem 2. Then write a structural-style VHDL code for an
8-bit incrementor using generate statements. Write a testbench to simulate
3)Write VHDL code for an n-bit incrementor circuit. Write a testbench to
simulate your incrementor for n=16, 32, and 64.

Lilmiss, Jul 19, 2005

2. ### Mike TreselerGuest

Lilmiss wrote:

> 2)Write a behavioral-style VHDL code for a 1-bit incrementor circuit as
> described in Problem 2.

n := n + 1;

Check the back of the book for the odd numbered problems.

-- Mike Treseler

Mike Treseler, Jul 19, 2005

3. ### Ralf HildebrandtGuest

Lilmiss wrote:

> If anyone provide me with vhdl source code for any of the following:
> 1) Design a ...

work and are trapped by a (small) error.

I will suggest only one thing:

library IEEE;
use IEEE.numeric_std.all;

This provides arithmetic operations on unsigned and signed vectors.

Ralf

Ralf Hildebrandt, Jul 19, 2005
4. ### LilmissGuest

Hi again,

Well I tried working on them again, but I'm still stuck at the last
question. I managed to write this code...Could you provide any suggestions
for improving it?

Generate:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

Entity incrementer_st is
generic(width : positive);
port(A : in std_logic_vector (width-1 downto 0) ;
C0 : in std_logic;
Cn : out std_logic;
S : out std_logic_vector(width-1 downto 0));
End incrementer_st;

architecture incrementer_st of incrementer_st is
component incrementer
port ( A : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
signal C : std_logic_vector(0 to width);
begin
g1 : for b in 0 to width-1 generate
U1: incrementer port map(A=>A(b), Cin=> C(b), S=>S(b), Cout=>C(b+1));
end generate;

C(0) <= C0;
Cn <= C(width);
end incrementer_st;

--Also, could you clarify the difference between generic and generate
statements (silly question I know)

10x

Lilmiss, Jul 23, 2005
5. ### jamesGuest

On Sat, 23 Jul 2005 13:28:40 -0400, "Lilmiss"
<> wrote:

>+<Hi again,
>+<
>+<Well I tried working on them again, but I'm still stuck at the last
>+<question. I managed to write this code...Could you provide any suggestions
>+<for improving it?
>+<
>+<
>+<Generate:
>+<
>+< library IEEE;
>+<use IEEE.STD_LOGIC_1164.all;
>+<
>+<
>+<Entity incrementer_st is
>+< generic(width : positive);

******

First off you have declared width and assigned an attribute but no
value has been assigned. How wide is width? 5 bits, 15 bits, 32 bits?

>+< port(A : in std_logic_vector (width-1 downto 0) ;
>+< C0 : in std_logic;
>+< Cn : out std_logic;
>+< S : out std_logic_vector(width-1 downto 0));
>+< End incrementer_st;
>+<
>+<
>+<
>+<architecture incrementer_st of incrementer_st is

******

What are you trying to do with the code below?
Instantiate or describe an architecture?

>+<component incrementer
>+<port ( A : in STD_LOGIC;
>+<Cin : in STD_LOGIC;
>+<S : out STD_LOGIC;
>+<Cout : out STD_LOGIC);
>+<end component;
>+<signal C : std_logic_vector(0 to width);
>+<begin
>+< g1 : for b in 0 to width-1 generate
>+< U1: incrementer port map(A=>A(b), Cin=> C(b), S=>S(b), Cout=>C(b+1));
>+< end generate;
>+<
>+< C(0) <= C0;
>+< Cn <= C(width);
>+<end incrementer_st;
>+<
>+<
>+<--Also, could you clarify the difference between generic and generate
>+<statements (silly question I know)
>+<
>+<10x

*******

Generics are used to set default values to signals and ports. They are
declared and assigned in the entity declaration section before port
declarations. An example would be to use generics to set the widths of
busses, bit sizes of registers and others. If you need to change the
widths, you just change the genrics and the rest of the code is
changed. Handy item.

Generate is used to duplicate sections of code or library entities.
Such a case for using generate would be in the creation of a nbit