help with verilog code

Discussion in 'VHDL' started by a, Feb 3, 2006.

  1. a

    a Guest

    wht happens with this code - can u tell me wat it wud synthesise to

    always@(*)
    begin
    a=x;
    if(z1)z=a|x1;
    if(z2)z=x2;
    end


    thanks
     
    a, Feb 3, 2006
    #1
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